Provided is a three-dimensional integrated circuit. The three-dimensional integrated circuit includes: a first die having a first surface and a second surface opposite each other; and a second die vertically stacked on the first surface of the first die. The first die includes: a functional block arranged on the first surface of the first die; and a plurality of conductive terminals arranged on the functional block and electrically connecting the first die to the second die. The plurality of conductive terminals include a plurality of edge conductive terminals arranged on an edge region of the functional block, and the plurality of edge conductive terminals are each spaced apart from a boundary of the functional block by a first distance that is greater than or equal to a minimum distance between the plurality of conductive terminals.

A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures. The microelectronic device further comprises a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising a sub word line driver region comprising complementary metal-oxide-semiconductor (CMOS) circuits vertically overlying and within a horizontal area of the staircase structure, and conductive contact structures vertically extending between steps of the staircase structure and the sub word line driver region. Related memory devices, electronic systems, and methods are also described.

The present disclosure provides a semiconductor package structure and a fabrication method thereof. The semiconductor package structure includes: a plurality of first semiconductor chips arranged as being stacked along a first direction, wherein the first semiconductor chip includes at least one conductive structure; the conductive structure includes a first connection structure and a second connection structure both extending along the first direction, and an interconnection structure located between the first connection structure and the second connection structure in the first direction; and the interconnection structure is connected with both the first connection structure and the second connection structure; and a first hybrid bonding layer located between two adjacent ones of the first semiconductor chips in the first direction, wherein the first hybrid bonding layer includes at least one first bonding structure coupled with the conductive structures in the two adjacent ones of the first semiconductor chips.

A 3D semiconductor device including: a first level including a first single crystal layer, a memory control circuit, the memory control circuit including first transistors, a first, second, and third metal layer, where connection of the first transistors includes any of the three metal layers; second transistors disposed atop the first level; third transistors are atop the second transistors; a fourth metal layer is atop the third transistors; a memory array including word-lines and memory cells, includes at least four memory mini arrays, where each of the memory cells includes at least one of the second transistors or the third transistors, a connection path from the fourth metal to the third metal which includes a via thru the memory array; and a semiconductor die atop and bonded to the first level which includes second transistors, at least one alignment mark positioned toward an edge of the die.

A structure is disclosed. The structure can include a first processor die, a second processor die, a first memory unit, and a connecting element. The second processor die can be laterally spaced from the first processor die. The first memory unit can be disposed vertically above the first processor die. The connecting element can be disposed vertically to the first processor die and the second processor die. The connecting element can include a conductor electrically connecting the first processor die and the second processor die.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. A semiconductor structure includes a first chip. The first chip includes a first interconnect layer, a first conductive layer disposed on the first interconnect layer, a first dielectric layer covering the first conductive layer, and a first bonding pad embedded in the first dielectric layer and extending into the first conductive layer. The method of manufacturing the semiconductor structure includes the following operations. A first conductive layer is formed on a first interconnect layer. A first dielectric layer is formed on the first conductive layer and the first interconnect layer. The first dielectric layer is etched to form a first trench on the first conductive layer. A portion of the first conductive layer is etched to form a second trench. A first bonding pad is formed in the second trench.

Provided is a semiconductor device including a peripheral circuit structure comprising peripheral circuits and a cell array structure overlapping the peripheral circuit structure and comprising first and second cell array regions and a connection region therebetween in a first direction, the cell array structure including a buried insulating pattern in the connection region, the buried insulating pattern having first and second side surfaces facing each other in the first direction and a third side surface connecting the first and second side surfaces, a stack including vertically stacked conductive patterns, each of the conductive patterns including a horizontal portion parallel to the first direction and a pad portion inclined with respect to the horizontal portion, and cell contact plugs connected to the pad portions of the conductive patterns, respectively, and the pad portion of each conductive pattern being on the first, second, and third side surfaces of the buried insulating pattern.

A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

A microelectronic device includes a memory array structure, an additional memory array structure, and a control circuitry structure. The memory array structure includes memory cells respectively including a vertical channel access device and a storage node device coupled to the vertical channel access device. The additional memory array structure vertically overlies the memory array structure and includes additional memory cells respectively including an additional vertical channel access device and an additional storage node device coupled to the additional vertical channel access device. The control circuitry structure vertically overlies and is bonded to one or more of the memory array structure and the additional memory array structure. The control circuitry structure includes control logic circuitry coupled to the memory cells of the memory array structure and the additional memory cells of the additional memory array structure. Related memory devices and electronic systems are also described.

Methods, systems, and devices for polymer material gap-fill for hybrid bonding in a stacked semiconductor system are described. A stacked semiconductor may include a first semiconductor die on a semiconductor wafer. A polymer material may be on the semiconductor wafer and may at least partially surround the first semiconductor die. A silicon nitride material may be on the first semiconductor die and on the polymer material. And a second semiconductor die may be hybrid bonded with a bonding material on the silicon nitride material.