Embodiments provide a fabricating method, a semiconductor structure, and a semiconductor device. The method includes: providing a plurality of chips, each of the chips includes an element region and a scribe line region arranged in a first direction; stacking the chips to form a chip module, where a stacking direction of the chips is a second direction perpendicular to the first direction, the element regions of the chips are overlapped with each other, and the scribe line regions of the chips are overlapped with each other; planarizing a side surface of each of the scribe line regions distant from the element region after the chip module is formed, to remove at least part of the scribe line regions and expose the power supply wiring layer; and forming a pad on the side surface planarized, where the pad is connected to the power supply wiring layer.

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a conductor/insulator stack over a substrate, configuring memory cells through the conductor/insulator stack, forming a conductive layer, removing a portion of the conductive layer to form an opening in the conductive layer, depositing a dielectric material in a space of the opening, and forming an airgap in the space.

A semiconductor package device includes a first semiconductor structure, a second semiconductor structure, and a non-metal dopant. The first semiconductor structure includes a first dielectric bonding layer and a first conductive bonding feature disposed in the first dielectric bonding layer. The second semiconductor structure includes a second dielectric bonding layer bonded to the first dielectric bonding layer and a second conductive bonding feature disposed in the second dielectric bonding layer. The first conductive bonding feature is bonded to the second conductive bonding feature to form an interface therebetween. The non-metal dopant is disposed in at least one of the first conductive bonding feature and the second conductive bonding feature.

A semiconductor device manufacturing method includes forming a first film containing a first device on a first substrate, forming a second film containing a semiconductor layer on a second substrate, and changing the semiconductor layer into a porous layer. The method further includes forming a third film containing a second device on the second film, and bonding the first substrate and the second substrate to sandwich the first film, the third film, and the second film therebetween. The method further includes separating the first substrate and the second substrate from each other at a position of the second film.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Decoder circuit, memory device, and control method are disclosed. The decoder circuit includes a decoding circuit and a power supply control circuit including: a first transistor, its input is connected to a low-level voltage node, and its output outputs a first ground voltage; a second transistor, its input is connected to a high-level voltage node, and its output outputs a first voltage; and a reverse circuit, its input receives a semiconductor component enabling signal, and its output is connected to the control terminal of one of the first or second transistor; and the control terminal of the first or second transistor not connected to the reverse circuit receives the semiconductor component enabling signal. The decoding circuit includes sub-circuits, wherein a power supply interface of sub-circuit is connected to the output of second transistor, or a grounding interface of sub-circuit is connected to the output of first transistor.

A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.

A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction.