A memory device includes a memory layer and a circuit layer. The memory layer includes first to third regions arranged in a first direction. The circuit layer includes first and second transfer regions, and first and second sense amplifier regions. The first and second transfer regions are shifted in the first direction and arranged in a second direction. In a third direction, the first sense amplifier region overlaps the first region, and the second sense amplifier region overlaps the second region. The first sense amplifier region and the first transfer region are arranged in the first direction, and the second sense amplifier region and the second transfer region are arranged in the first direction.

The present invention provides a semiconductor device and a method of fabricating the device, in which in each adjacent pair of semiconductor substrates, a first semiconductor substrate is bonded to a backside of a second semiconductor substrate, and external connection terminals are adjacent, and electrically connected, to a second semiconductor substrate. In each adjacent pair of semiconductor substrates, there is a first dielectric layer containing plug structures, which electrically connect the semiconductor substrates to each other. With this arrangement, power from an external power source can be supplied to each semiconductor substrate through a power transmission path constructed of plug structures. At least some first dielectric layers each contain a DTC structure, which is electrically connected to second ends of the plug structures in specific first dielectric layer. During propagation of an electrical signal through the plug structures, it passes through the DTC structure before arriving at downstream semiconductor substrate.

An electronic system includes a first device and a second device bonded to the first device. The first device includes: a semiconductor substrate with an opening; a stack having metal layers and conductive vias; and a conductive layer including aluminum having a first face in contact with the stack and a second face, opposite the first face, that is partially exposed through the opening. The metal layers and the conductive vias of the stack are made of a conductive material different from aluminum.

A semiconductor package may include a first semiconductor die having a first width; a second semiconductor die on the first semiconductor die, the second semiconductor die having a second width that is smaller than the first width; and a mold layer at least partially covering a side surface of the second semiconductor die, and a top surface of the first semiconductor die, wherein the first semiconductor die comprises at least one first detection pattern, the at least one first detection pattern being on the top surface of the first semiconductor die and in contact with a bottom surface of the mold layer.

According to one embodiment, a memory device includes: a first substrate, a second substrate, and wiring layers arranged apart from each other in this order in a first direction, the wiring layers being arranged apart from each other in the first direction; a memory pillar extending in the first direction and having portions intersecting with respective wiring layers to function as memory cells; a conductive film provided on a surface of the second substrate alongside the wiring layers; a first contact extending in the first direction at a side of the wiring layers relative to the conductive film and in contact with the conductive film; and a second contact extending in the first direction to intersect with the second substrate at a side of the first substrate relative to the conductive film, and in contact with the conductive film.

A semiconductor device including a transistor region including vertical transistors arranged in an array to form a memory array area, and word lines connected to the vertical transistors. A capacitor region is formed within the memory array area above the transistor region and including vertical capacitors vertically connected to the vertical transistors through capacitor contacts. Bit lines are formed below the transistor region and vertically connected to the vertical transistors, the word lines and bit lines being arranged to form a matrix configuration within the memory array area. Backside contacts are formed within the memory array area, each backside contact connected to either a respective word line or a respective bit line and extending vertically to below the bit lines.

Bonded die structures and methods of fabrication thereof that provide reduced defects and higher reliability. A laser grooving process may be used to precut bonded device structures prior to a final dicing process. The laser grooving process may form relatively deep grooves in the bonded device structure that may extend beyond the bonding interface between a first device structure and a second device structure. A final dicing process along the precut grooves may be used to separate individual bonded die structures. Because the dicing occurs along the deep precut grooves that extend through the bonding interface between the stacked device structures, the dicing blade may not cut through or come into contact with the bonding interface. This may result in in reduced mechanical stress, which may decrease the occurrence of delamination defects between the device structures and thereby provide improved reliability and increased yields.

Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.

A semiconductor package including a redistribution structure, a first capacitor die on the redistribution structure, a 3D integrated circuit structure on the redistribution structure, and next to the first capacitor die, a logic die on the first capacitor die, and on the 3D integrated circuit structure;, and a memory stack on the 3D integrated circuit structure. The 3D integrated circuit structure including a second capacitor die and a buffer die on the second capacitor die.

A structure includes a first substrate, a second substrate, and an interface region. The first substrate includes a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion. The second substrate includes a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The interface region is between the first layer and the second layer and includes at least one electrically conductive polymer material.