Embodiments provide a semiconductor structure and a fabricating method. The method includes: providing a substrate including a first type region and a second type region; a first insulation layer and a first initial gate structure being provided on the substrate of the first type region, and a second insulation layer and a second initial gate structure being provided on the substrate of the second type region; and simultaneously etching the first initial gate structure and the second initial gate structure multiple times to form a first gate structure and a second gate structure, an orthographic projection of a bottom of the first gate structure on the substrate being positioned in an orthographic projection of a top of the first gate structure on the substrate, where after a first etching process, a top surface of the first insulation layer positioned in the first type region is not exposed to outside.

A device comprises a stacked transistor structure and a shared gate structure. The stacked transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and which is disposed over the first transistor. The shared gate structure comprises a first metal gate structure of the first transistor, a second metal gate structure of the second transistor, and a metallic connection layer. The second metal gate structure is embedded in the first metal gate structure with a dielectric layer disposed between the first metal gate structure and the second metal gate structure. The metallic connection layer electrically connects upper regions of the first metal gate structure and the second metal gate structure.

An exemplary semiconductor structure includes first, second and third field effect transistor (PET) stack on a substrate. Each of the first, second and third FET stacks includes a top and a bottom transistor. Each transistor has a channel region, a gate insulator and a gate work function layer. Each of the gate work function layers in the top transistors of the first, second and third FETs having a different composition.

A device comprises a stacked transistor structure, and a shared gate structure. The stacked transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and disposed over the first transistor. The shared gate structure comprises a first metal gate structure of the first transistor, and a second metal gate structure of the second transistor. The second metal gate structure is embedded in the first metal gate structure.

Embodiments include a semiconductor structure having a first lower transistor and a second lower transistor. Upper transistors are formed above the first and second lower transistors, the first lower transistor having a first work function material, the second lower transistor having a second work function material different from the first work function material. A portion of the second work function material extends below a bottom surface of the first work function material.

A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

The present invention provides a preferentially orientated electrode film and preparation methods thereof, relating to the technical field of thin film preparation, comprising a silicon-based substrate and a primary seed layer, a secondary seed layer and a bottom electrode layer grown sequentially on said substrate; said primary seed layer being an A.sub.xB.sub.1-xN film or an A.sub.3-xB.sub.1-xN film, wherein ACu, Fe; BPd, Pt; Ox1; in which said secondary seed layer is made of one or more of the following films: chromium nitride film, titanium nitride film, tantalum nitride film, magnesium oxide film; and said bottom electrode layer is made of one or more of the following films: a platinum film, a titanium nitride film, a gold film, a strontium ruthenate film, or a niobium doped strontium titanate film, which has a preferential orientation in the (00/) crystallographic direction, to solve the problem that the existing films with (00/) preferential orientations are not obtainable on a Silicon based substrate.

Provided are semiconductor devices, e.g., transistors, and methods of manufacturing semiconductor devices which achieve NMOS band edge with low resistivity and having improved device performance and reliability. Provided are materials that can be used as effective N-metal films for transistors. Instead of conventional titanium aluminum carbide (TiAlC) based N-metal films, provided are binary/ternary metal carbide films and metal silicide films that may be used as N-metal films with no/minimal high-k (HK) capping layer required.

A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.