A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

A semiconductor device includes first and second sheet patterns spaced apart from each other on a first region of the substrate, a first gate electrode extending between the first and second sheet patterns, third and fourth sheet patterns spaced apart from each other on a second region of the substrate, and a second gate electrode extending between the third and fourth sheet patterns. The first gate electrode includes a first work function controlling film, which is between the first and second sheet patterns, and a first filling conductive film on the first work function controlling film. The second gate electrode includes a second work function controlling film, which is between the third and fourth sheet patterns, and a second filling conductive film on the second work function controlling film. A distance between the third and fourth sheet patterns is greater than a distance between the first and second sheet patterns.

Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The method includes forming first and second fin structures, the first fin structure includes a first plurality of semiconductor layers, and the second fin structure includes a second plurality of semiconductor layers. The method further includes depositing a gate dielectric layer around a portion of each semiconductor layer of the first and second pluralities of semiconductor layers, depositing a sacrificial layer on the gate dielectric layer, removing a first portion of the sacrificial layer disposed on a first portion of the gate dielectric layer around the first plurality of semiconductor layers, selectively depositing a first work function layer on the portion of the gate dielectric layer, and removing a second portion of the sacrificial layer disposed on a second portion of the gate dielectric layer around the second plurality of semiconductor layers.

A method of fabricating a semiconductor device includes forming a gate structure over a channel region, wherein the gate structure comprises a gate stack and gate spacers along sidewalls of the gate stack. The method further includes removing the gate stack to expose the channel region. The method further includes depositing a gate dielectric layer over a bottom of the opening. The method further includes forming a doped work function material layer over the gate dielectric layer, wherein the doped work function material layer has a variable dopant concentration, and the doped work function material layer comprises dopants throughout an entirety of the doped work function material layer.

Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.

Embodiments of the disclosure relate to methods of depositing seam-free gapfill. In some embodiments, the gapfill consists of titanium nitride. The gapfill methods comprise forming a first layer and a second layer. The firs layer is formed without treatment or densification, while the second layer is formed with periodic treatment. The resulting gapfill in advantageously seam-free.

Disclosed are methods and systems for depositing layers comprising a Group 13 element on a surface of a substrate via contacting the substrate with at least a vapor-phase first precursor and a vapor-phase second precursor comprising an alkyl halide. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, and metal-insulator-metal (MIM).

A method of forming a semiconductor device comprises the following steps. A multi-layer stack is formed over a substrate. The multi-layer stack comprises alternately stacked first semiconductor layers and second semiconductor layers. A dielectric protective layer is formed over the multi-layer stack. Gate spacers are formed over the dielectric protective layer. A first portion of the dielectric protective layer is removed from a top surface of the multi-layer stack, while leaving second portions of the dielectric protective layer under the gate spacer. The first semiconductor layers are replaced with a metal gate stack. A gate contact is formed over the metal gate stack.