A semiconductor package includes: a substrate including a first region and a second region at least partially surrounding the first region in a plane defined by first and second horizontal directions, wherein the substrate has a first surface and a second surface opposed to the first surface; a wiring pattern disposed on the first surface of the substrate; a first recess formed on the second surface of the substrate and in the second region of the substrate; a back side insulating layer disposed on the second surface of the substrate, wherein the back side insulating layer fills an inside of the first recess; a through via penetrating through the first region of the substrate and the back side insulating layer, wherein the through via connects to the wiring pattern; and a second recess formed in the back side insulating layer and on the first recess.

One aspect of the present disclosure pertains to a package structure. The package structure includes a die bonded to a substrate, where a plurality of first channels are formed on a top surface of the die; a lid bonded to the substrate and over the die; and a thermal interface material (TIM) disposed between and contacting the lid and the die, where the thermal interface material fills the first channels.

A semiconductor package includes a substrate including a wiring; a chip stack including a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips has upper and lower surfaces, opposite to each other, front and rear surfaces, opposite to each other, left and right surfaces, opposite to each other, and connection pads disposed on the upper surface adjacent to the front surface; bonding wires electrically connecting the connection pads to the wiring of the substrate; a plurality of attachment films disposed on the lower surface of each of the plurality of semiconductor chips; a mold layer covering the chip stack and the bonding wires; and connection bumps disposed below the substrate, and electrically connected to the wiring, wherein at least one of the plurality of attachment films covers the rear surface of at least one semiconductor chip among the plurality of semiconductor chips.

Electronic structures and methods of assembly are described in which a lid with pocket sidewalls is mounted on a routing substrate such that the pocket sidewalls laterally surround an electronic component and provide a barrier to outflow of the thermal interface layer outside of the pocket sidewalls, and in particular a thermal interface layer including a liquid metal film.

A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.

A package structure is provided. The package structure includes a device die bonded to a package substrate via a plurality of connectors. The package structure includes a dummy die bonded to the package substrate via a plurality of dummy connectors and disposed adjacent to the device die. The dummy die includes a base portion, an upper portion bonded to the base portion, and an edge molding material formed over the base portion and surrounding the upper portion. The package structure also includes a package molding material over the package substrate and around the dummy die and the device die. The Young's modulus of the edge molding material is less than the Young's modulus of the package molding material.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

A semiconductor device can include: a semiconductor chip including a first and second surface, a first electrode on the first surface, an active area on the second surface, a second electrode on the second surface, and a third electrode on the second surface; a first conductive member in the active area of the semiconductor chip and electrically connected to the semiconductor chip; a second conductive member in a second area and isolated from the first conductive member, the second area an area in which, when viewed from above, with respect to a first area of the active area in which the first conductive member is not provided, circles sharing centers of shortest distances between an outer periphery of the first conductive member and an outer periphery of the active area can be drawn largest in the first area; and a lead terminal connected to the first conductive member.

A semiconductor package includes a buffer die; a plurality of first core dies and a plurality of second core dies, stacked on a first surface of the buffer die in a first direction; a bridge buffer die on the plurality of first core dies and the plurality of second core dies; and a plurality of third core dies and a plurality of fourth core dies, stacked on a surface of the bridge buffer die in the first direction, in which the plurality of first core dies are at positions symmetrical with positions of the plurality of second core dies with respect to a center line in a second direction dividing the top surface of the buffer die into two, and in which the plurality of third core dies overlap the plurality of first core dies in the first direction.