A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

A semiconductor package includes a substrate, a bridge die, a first sub-package and a second sub-package, and a plurality of connectors. The bridge die is adhered on a first side of the substrate by an adhesive. The first sub-package and the second sub-package are disposed on the substrate and electrically coupled to the substrate and the bridge die, where the bridge die is disposed between the first sub-package and the substrate. The plurality of connectors are disposed on a second side of the substrate, the first side is opposite to the second side, where the plurality of connectors is electrically coupled to the substrate.

The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a substrate, an electronic element, an underfill layer, and a protective structure. The electronic element is disposed on the substrate. At least a portion of the underfill layer is disposed between the substrate and the electronic element. A thickness of the underfill layer is not greater than a height from a surface of the substrate to an upper surface of the electronic element. The protective structure is disposed on the substrate and adjacent to the underfill layer. The electronic device and the manufacturing method thereof of the disclosure may effectively control an area of the underfill layer.

A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.

A semiconductor package includes a substrate including a wiring; a chip stack including a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips has upper and lower surfaces, opposite to each other, front and rear surfaces, opposite to each other, left and right surfaces, opposite to each other, and connection pads disposed on the upper surface adjacent to the front surface; bonding wires electrically connecting the connection pads to the wiring of the substrate; a plurality of attachment films disposed on the lower surface of each of the plurality of semiconductor chips; a mold layer covering the chip stack and the bonding wires; and connection bumps disposed below the substrate, and electrically connected to the wiring, wherein at least one of the plurality of attachment films covers the rear surface of at least one semiconductor chip among the plurality of semiconductor chips.

Electronic structures and methods of assembly are described in which a lid with pocket sidewalls is mounted on a routing substrate such that the pocket sidewalls laterally surround an electronic component and provide a barrier to outflow of the thermal interface layer outside of the pocket sidewalls, and in particular a thermal interface layer including a liquid metal film.

A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.