A semiconductor package includes a substrate, a semiconductor device bonded over the substrate, a coefficient of thermal expansion (CTE) adjusting component bonded over the substrate and at least partially surrounding the semiconductor device, and an underfill material disposed between the substrate and the semiconductor device and encapsulating side surfaces of the semiconductor device and the CTE adjusting component, wherein a CTE of the CTE adjusting component is substantially lower than a CTE of the underfill material at a temperature being substantially equal to or higher than 200 Celsius.

An electronic package and a manufacturing method thereof are provided, the electronic package has at least one dam at the edge thereof to prevent packaging material from overflowing to the bottom of the electronic package, so that the packaging material is free from contacting the conductive components on the bottom of the electronic package, thereby avoiding problem of non-wetting of the conductive components when the conductive components are subsequently reflowed.

Chip packages having thermal interface retaining structures and methods for fabricating the same are disclosed herein. In one example, a chip package including a substrate, an integrated circuit (IC) die, a first metal thermal interface material (MTIM), a lid, and a retaining structure. The substrate includes a bottom surface facing a top surface of the substrate. The first MTIM is disposed on a top surface of the IC die. The lid is disposed over the IC die and has a bottom side contacting the first MTIM. The thermal interface retaining structure is disposed outwardly of the first MTIM and captures the first MTIM on the top surface of the IC die.

In examples, a semiconductor package comprises a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate. The package includes a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region. The package also includes conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuity region. The package further comprises a first support member coupled to the device side of the semiconductor die and extending toward the substrate and not touching the substrate or a second support member coupled to the substrate. The package also includes a ring on the substrate and encircling the bond pads and a glob top member covering the semiconductor die and a portion of the substrate circumscribed by the ring. The package also includes a mold compound covering the glob top member and the substrate.