The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.

A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.

A semiconductor device includes a die and a coreless embedded trace substrate (ETS). The die has an embedded circuit. The die can include ports on a surface of the die coupled to the embedded circuit of the die. The coreless ETS can underlie the die. The ETS can include a cavity having circuit components embedded in the cavity, ports on a surface of the ETS coupled to the circuit components embedded in the cavity and solder balls coupling the ports of the ETS to the ports of the die. In some examples, the embedded circuit in the die is a switching power field effect transistor (FET), in other examples, a bulk acoustic wave (BAW) resonator. The circuits embedded in the cavity, in some instances, include a radio frequency (RF) network for the BAW resonator, in other examples, include passive circuit components.

A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 m/1.5 m. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.

A high-frequency module includes a first module substrate including first and second major surfaces, and a second module substrate including third and fourth major surfaces. The first major surface (faces the second major surface. Electronic components are disposed between the second and third major surfaces, on the first major surface, and on the fourth major surface. External connection terminals are disposed on the fourth major surface. A recess is formed in the first major surface. The electronic components include a first electronic component and a second electronic component (shorter in height than the first electronic component. The first electronic component is disposed in the recess, and the second electronic component is disposed in a region outside of the recess on the first major surface.

A semiconductor device has a substrate and an electrical component disposed over the substrate. A first encapsulant is deposited over the electrical component and substrate. A first shielding layer with a graphene core shell is formed on a surface of the first encapsulant. A second encapsulant is deposited over the first encapsulant and first shielding layer. A second shielding layer is formed over the second encapsulant. The first shielding layer is formed at least partially in an opening of the first encapsulant. The graphene core shell has a copper core. The first shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the first shielding layer to form an electrical path. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.

A package structure includes forming a semiconductor substrate for RF application, a first ultra thick metal disposed over the semiconductor substrate, a second ultra thick metal disposed over the first ultra thick metal, and a bump structure directed formed on the second ultra thick metal. The second ultra thick metal is coupled to the first ultra thick metal. A patterned ground shield (PGS) structure may be formed over the semiconductor substrate and below the first ultra thick metal.

A method of manufacturing a high-frequency device includes mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer covering the first chip on the metal base, exposing an upper surface of the first pillar from the insulator layer, and forming a first wiring connected to the first pillar on the insulator layer and transmitting a high-frequency signal.

Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.