Patent classifications
H10P70/23
METHOD OF FORMING HIGH VOLTAGE TRANSISTOR AND STRUCTURE RESULTING THEREFROM
A semiconductor structure includes: a semiconductor substrate; a gate dielectric layer over the semiconductor substrate; and a gate electrode over the gate dielectric layer. The gate dielectric layer includes a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion includes a third portion including nitrogen and enclosed by the first portion.
Wafer transfer method and wafer transfer apparatus
A wafer transfer method for forming a second work unit by transferring a wafer of a first work unit including a first ring frame, a first adhesive tape, and the wafer to a second adhesive tape includes sandwiching a claw body between the first ring frame and a second ring frame, affixing the second adhesive tape to a surface of the wafer which surface is not affixed to the first adhesive tape, holding the wafer by the second ring frame via the second adhesive tape, and peeling off the first adhesive tape from the wafer.
THERMAL ATOMIC LAYER ETCH WITH RAPID TEMPERATURE CYCLING
Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.
Halogen-free molybdenum-containing precursors for deposition of molybdenum
Exemplary methods of semiconductor processing, such as methods of depositing a molybdenum-containing material on a substrate, may include providing a molybdenum-containing precursor to a processing region of a semiconductor processing chamber in which the substrate is located. The molybdenum-containing precursor may include a molybdenum complex according to Compound I: ##STR00001##
R may be methyl or ethyl, R may be methyl or ethyl, R may be methyl, ethyl, or propyl, and n may be equal to 1 or 2. Contacting the substrate with the molybdenum-containing precursor may deposit the molybdenum-containing material on the substrate.
Semiconductor wafer cleaning apparatus
A semiconductor wafer cleaning apparatus is provided. The semiconductor wafer cleaning apparatus includes a spin base, a spindle extending through the spin base, and a clamping member covering the spin base. The spindle includes a mounting part and a supporting part disposed on the mounting part. The mounting part includes an inner projection, the supporting part includes a conical projection, and the conical projection is surrounded by the inner projection. The semiconductor wafer cleaning apparatus further includes a first sealing ring disposed between the spin base and the mounting part.
Substrate processing apparatus, non-transitory computer-readable recording medium, substrate processing method and method of manufacturing semiconductor device
There is provided a technique capable of cleaning a film deposited on an outer peripheral portion of a substrate placing surface of a substrate support. According to one aspect thereof, a substrate processing apparatus includes: a process chamber where a product substrate is processed; a substrate support provided in the process chamber and provided with a substrate placing surface whereon the product substrate is placed; a process gas supplier wherethrough a process gas is supplied into the process chamber while the product substrate being placed on the substrate placing surface; and a cleaning gas supplier wherethrough a cleaning gas is supplied into the process chamber while a dummy substrate being placed on the substrate placing surface. An outer peripheral portion of the dummy substrate is out of contact with the substrate placing surface in a state where the dummy substrate is placed on the substrate placing surface.
Conformal boron doping method for three-dimensional structure and use thereof
A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.
HARD MASK TRIMMING IN METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process. The lateral etching process includes a radical etching process and a chemical etching process. Alternatively, the lateral etching process includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.