A method includes receiving a first notification that a process chamber of a baking apparatus entered an idle state, determining that a low-flow-rate (LFR) mode can be started, and providing an incoming gas to the process chamber. The incoming gas includes a first portion of a supply gas. The method further includes setting a flow rate of the incoming gas to an idle incoming flow rate, receiving a second notification that the process chamber entered an active state, determining that a high-flow-rate (HFR) mode can be started, and setting the flow rate of the incoming gas to a process incoming flow rate. The process incoming flow rate is greater than the idle incoming flow rate.

A method of manufacturing a semiconductor device includes positioning a substrate on a hot plate in a chamber, and heating the substrate on the hot plate to volatilize contaminant particles on the substrate. The method further includes coupling the chamber to an external pump line through a locking mechanism. The locking mechanism is configured to couple a first adapter connecting to the chamber with a second adapter connecting to the external pump line. The method also includes detecting a coupling status between the first adapter and the second adapter using a sensor, and maintaining the locking mechanism based on the coupling status.

A method of manufacturing semiconductor devices, the semiconductor devices manufactured, and apparatuses for forming the semiconductor devices are described in which by-products from etching processes are independently heated separately from a semiconductor wafer. In embodiments a dielectric material is deposited into a trench over a semiconductor substrate and the dielectric material is recessed with an etching process. The etching process includes heating the semiconductor substrate and separately heating a by-product of the etching process.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Provided are nitride atomic layer etch including in situ generating a phosphoric acid on the surface of silicon nitride layer by reacting a phosphorus containing reactant with one or more oxidants. Phosphoric acid selectively etches silicon nitride layer over silicon oxide and/or silicon.

A method includes providing a workpiece. The workpiece includes a stack of channel layers and sacrificial layers, a dummy gate structure disposed over the stack, and a source/drain trench adjacent to the stack and the dummy gate structure. The method further includes replacing the sacrificial layers with a first dummy layer and a second dummy layer. The second dummy layer is spaced apart from the channel layers by the first dummy layer. The method further includes selectively and partially recessing the first dummy layer and the second dummy layer to form inner spacer recesses among the channel layers, forming inner spacer features in the inner spacer recesses, forming a source/drain feature in the source/drain trench, and replacing the dummy gate structure, the first dummy layer, and the second dummy layer with a metal gate structure.

A method of the present disclosure includes forming a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack over a channel region of the fin-shaped structure, recessing a source/drain region of the fin-shaped structure to form a trench, removing the sacrificial layers in the channel region to release the channel layers as channel members, partially filling a space vertically stacked between adjacent two of the channel members with a dielectric dummy layer, performing a treatment to expand the dielectric dummy layer to fully fill the space, laterally recessing the dielectric dummy layer to form recesses, forming inner spacers in the recesses, forming a source/drain feature in the trench, removing the dummy gate stack, removing the dielectric dummy layer to release the channel members, and forming a gate structure to wrap around the channel members.

A method includes removing a dummy gate stack to form a trench between gate spacers, and removing a sacrificial layer contacting a semiconductor region. The sacrificial layer and the semiconductor region are in the trench. The method further includes depositing a gate dielectric into the trench and on the semiconductor region, depositing a liner on the gate dielectric, depositing a fluorine-containing layer over the liner, performing a drive-in process to drive fluorine in the fluorine-containing layer into the gate dielectric, and depositing a conductive layer over the gate dielectric.

Provided is a semiconductor device manufacturing method including a process of annealing a semiconductor wafer in a state in which a supported portion on a lower surface of the semiconductor wafer is supported by using a supporting portion, wherein the supported portion includes one or a plurality of supporting portions and the supporting portion includes one or a plurality of supporting portions, the method comprising: forming impurity regions including a first impurity in a region which is overlapped with the supported portion in a top view and which is apart from an edge of the semiconductor wafer; annealing the semiconductor wafer in a state in which the lower surface of the semiconductor wafer is supported by the supporting portion; and removing the impurity regions by removing a region including the lower surface of the semiconductor wafer.

A semiconductor substrate is configured for dicing into separate die or individual semiconductor devices. The semiconductor substrate can comprise silicon, silicon carbide, or gallium nitride. A dicing grid bounds each semiconductor device on the semiconductor substrate. A die singulation process is configured to occur in the dicing grid. Material is coupled to the dicing grid. In one embodiment, the material can comprise carbon. A laser is configured to couple energy to the material coupled to the dicing grid. The energy from the laser heats the material. The heat from the material or the temperature differential between the material and the dicing creates a thermal shock that generates a vertical fracture in the semiconductor substrate that separates the semiconductor device from the remaining semiconductor substrate.