Provided are a composition including an oxidizing agent, a phosphoric acid, an organic acid, and an etching controller and having pH of 2.0 or less, wherein the oxidizing agent includes hydrogen peroxide, an iodine-containing compound, or any combination thereof, and the etching controller includes a hydroxyl-free and nitrogen-containing compound, a method of treating a metal-containing film using the composition, and a method of manufacturing an electronic device by using the composition.

A method for forming a semiconductor structure includes providing a base with a first area and a second area; patterning a first core material layer and forming first core layers; forming first spacers; patterning a second core material layer and forming second core layers; modifying the second core layers exposed in the second area to form third core layers having an etching selectivity ratio with remaining second core layers; forming second spacers covering sidewalls of the second core layers and third core layers; and patterning a target material layer using the second spacers and third core layers as a mask and forming first target structures and second target structures. The pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures. SAQP and SALELE processes are integrated. Redundant first target structures made by SAQP are removed without adding masks and process steps.

A biological sensing system, comprising a microelectrode array having a plurality of islands that are thermally isolated from each other and are interconnected by flexible nano-scale wires. An embedded complementary metal oxide semiconductor (CMOS) instrumentation amplifier and wireless communication circuitry may be operatively connected to the microelectrode array and embedded within input/output pads connected to the wires at the periphery of the array.

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.

A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.

A method includes: providing a substrate containing a first plurality of fins of a first polarity type, a second plurality of fins of a second polarity type, and a contiguous gate structure that extends over each of the first plurality of fins and second plurality of fins; and forming a first opening in the contiguous gate structure with a first cut between the first pair of fins of the first polarity type and a second opening in the contiguous gate structure with a second cut between the second pair of fins of the second polarity type via common etching operations; wherein performing the common etching operations includes forming the first opening with a first middle critical dimension (MCD) and the second opening with a second MCD, wherein the first MCD is larger than the second MCD.