To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.

A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

A semiconductor package includes a redistribution structure, a first semiconductor chip above the redistribution structure, a second semiconductor chip on, and offset relative to, the first semiconductor chip, a plurality of first conductive posts extending from a bottom surface of the second semiconductor chip to a top surface of the redistribution structure, a third semiconductor chip on the second semiconductor chip, a plurality of second conductive posts extending from a bottom surface of the third semiconductor chip to the top surface of the redistribution structure, and a molding layer between the top surface of the redistribution structure and the bottom surface of the third semiconductor chip.

A semiconductor package may include a first substrate, semiconductor dies stacked on the first substrate in a direction perpendicular to a top surface of the first substrate to have a stepwise structure, a mold layer disposed on the first substrate to cover the semiconductor dies, a second substrate disposed on the mold layer, and vertical conductive lines electrically connecting the semiconductor dies to the second substrate. The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.

Systems, devices, and methods for high die stack packages with secondary interposers are provided herein. A die stack package can include a first substrate, a first die stack carried by the first substrate, a second die stack carried by the first substrate, a second substrate carried by the first die stack and the second die stack, a third die stack carried by the second substrate, a fourth die stack carried by the second substrate, and one or more vertical wires electrically coupling the first substrate and the second substrate. Each of the first, second, third, and fourth die stacks can include a plurality of dies stacked in a cascading arrangement. In some embodiments, the first and second die stacks are each electrically coupled to the first substrate. In some embodiments, the first and second die stacks are each electrically coupled to the second substrate.

Systems, devices, and methods for high die stack packages with vertical die-to-die interconnects are provided herein. A die stack package can include a substrate, a lower die stack carried by the substrate, a spacer carried by the substrate, an upper die stack carried by the spacer, a plurality of wire bonds, and a plurality of vertical wires. The lower die stack can include a plurality of lower dies stacked in a cascading arrangement. The upper die stack can include a plurality of upper dies stacked in a cascading arrangement in a same direction as the plurality of lower dies. The wire bonds can electrically couple adjacent ones of the lower dies. An nth vertical wire can extend vertically between and electrically couple an nth upper die and an nth lower die. In some embodiments, the die stack package further includes an input-and-output extender carried by the substrate.

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

A semiconductor package of an embodiment includes: a wiring substrate having a first surface and a second surface on a side opposite to the first surface; at least one semiconductor chip provided in plurality at different heights from the first surface in a vertical direction; a sealing resin covering the first surface of the wiring substrate and surfaces of the at least one semiconductor chip; a layer formed over a top layer of the at least one semiconductor chip; and an external terminal provided on the second surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.