Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

A semiconductor package includes a wiring structure. A buffer die is disposed on the wiring structure. A logic die is disposed alongside the buffer die on the wiring structure. A first encapsulating material covers at least a portion of each of the buffer die and the logic die. A memory stack is disposed on the buffer die and is electrically connected to the buffer die. A bridge die is disposed so as to extend over at least a portion of each of the buffer die and the logic die, and is electrically connected to each of the buffer die and the logic die. A second encapsulating material covers at least a portion of each of the memory stack and the bridge die. The buffer die and the logic die are disposed at a level that is between those of the wiring structure and the bridge die.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first member. The second electrode includes first and second electrode regions. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial region. The second semiconductor region includes first to third semiconductor portions. At least a part of the third semiconductor portion is between the first semiconductor region and the second electrode region. The second semiconductor portion is between the first semiconductor portion and the third semiconductor region. The first member includes first and second regions.

A high electron mobility transistor includes a substrate, a barrier layer, a semiconductor layer and an insertion layer. The barrier layer is disposed on the substrate and includes aluminum gallium indium nitride. The semiconductor layer is disposed between the substrate and the barrier layer. The insertion layer is disposed between the semiconductor layer and the barrier layer, and includes aluminum gallium nitride.

Methods, systems, and devices for polymer material gap-fill for hybrid bonding in a stacked semiconductor system are described. A stacked semiconductor may include a first semiconductor die on a semiconductor wafer. A polymer material may be on the semiconductor wafer and may at least partially surround the first semiconductor die. A silicon nitride material may be on the first semiconductor die and on the polymer material. And a second semiconductor die may be hybrid bonded with a bonding material on the silicon nitride material.

An electronic device and associated methods are disclosed. In one example, the electronic device includes a photonic integrated circuit and an in situ formed waveguide. In selected examples, the electronic device includes a photonic integrated circuit coupled to an electronic integrated circuit, in a glass layer, where a waveguide is formed in the glass layer.

Disclosed is a stacked electronic device including a first and second bonded structure. The first bonded structure includes a first and second semiconductor element, each having a semiconductor region, a front side on one side of the semiconductor region including active circuitry, and a back side opposite the front side. The front side of the first semiconductor element is bonded and electrically connected to the front side of the second semiconductor element. The second bonded structure includes a third and fourth semiconductor element, which can include similar components to the first and second semiconductor elements. The front side of the third semiconductor element is bonded and electrically connected to the front side of the fourth semiconductor element. The back side of the second semiconductor element is bonded and electrically connected to the back side of the third semiconductor element.

The glass for covering a semiconductor element contains: in mol %, as a glass composition, SiO.sub.2: 20% to 36%, ZnO: 8% to 40%, B.sub.2O.sub.3: 10% to 24%, Al.sub.2O.sub.3: 10% to 20%, and MgO+CaO: 8% to 22%, in which SiO.sub.2/ZnO is 0.6 or more and less than 3.3 in terms of a molar ratio, and a lead component is substantially not contained.

The glass for covering a semiconductor element contains: in mol %, as a glass composition, SiO.sub.2: 20% to 36%, ZnO: 8% to 40%, B.sub.2O.sub.3: 10% to 24%, Al.sub.2O.sub.3: 10% to 20%, and MgO+CaO: 8% to 22%, in which SiO.sub.2/ZnO is 0.6 or more and less than 3.3 in terms of a molar ratio, and a lead component is substantially not contained.

A semiconductor unit includes: a barrier layer including a first compound semiconductor; a channel layer including a second compound semiconductor, and bonded to the barrier layer at a first face; an insulation layer provided on a second face, of the barrier layer, that is on an opposite side of the first face, and having an opening section that exposes the barrier layer; a gate electrode provided to bury the opening section; a source electrode and a drain electrode that are provided on the second face of the barrier layer on both sides of the gate electrode with the gate electrode being interposed; and a material layer including a metal material or a semiconductor material, and provided in contact with the second face of the barrier layer between the gate electrode and the drain electrode.