Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.

Proposed is a method for fabricating a semiconductor device. The method includes a semiconductor structure provision step of providing a semiconductor structure including one or more channel layers each having an interfacial layer formed on a surface thereof, an interfacial layer surface activation step for activating a surface of the interfacial layer by treating the semiconductor structure with hydrogen plasma, and a dipole doping step for bonding a dipole-forming atom to the activated surface of the interfacial layer. According to the method, a dipole interface can be formed in a gate insulating layer through a simple process by doping dipole-forming atoms after activating the interfacial layer surface by hydrogen plasma treatment.

A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.

A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

A semiconductor device includes an amorphous fluorinated carbon thin film having a dielectric constant of 10 or more as a gate dielectric film. The semiconductor device includes: a substrate; source/drain regions arranged facing each other on the substrate; a gate electrode disposed on the substrate to apply an electric field; and a gate dielectric film interposed between the gate electrode and the substrate.

The disclosure provides for a semiconductor device, preferably a MOSFET transistor, having a EPI layer which is made of semiconductor material such as silicon. The EPI layer has a top surface and a bottom surface opposite to the front surface. The proposed MOSFET is a trench type transistor with the source-polysilicon element embedded in the trench formed in the substate.