A method for forming an integrated circuit. The method includes providing a semiconductor structure comprising: (i) two transistors, (ii) a gate on the channel of the transistor, (iii) contacts coupled to each transistor, (iv) a dielectric layer over the two transistors, the gate, and the contacts, (v) a first conductive line arranged within a first metallization level and extending along a first direction, (vi) a first conductive via connecting the first conductive line with a first contact of a transistor, and (vii) a second conductive via connecting the first conductive line with a second contact of a transistor. The method also includes recessing the first dielectric layer, providing spacers along the first conductive line, depositing a second dielectric layer on the first dielectric layer, forming an opening in the second dielectric layer and first dielectric layer, and providing a conductive material in the opening, thereby forming a third conductive via.

A method for semiconductor manufacturing includes removing an oxide layer disposed over a conductive feature, flowing a gallium precursor over the conductive feature, and depositing a metal over the conductive feature after flowing the gallium precursor. The conductive feature is adjacent to a dielectric feature. The metal is deposited selectively over the conductive feature relative to the dielectric feature.

The present disclosure describes a method for forming an interconnect structure. The method can include forming a first layer of insulating material on a substrate, forming a via recess within the layer of insulating material, filling the via recess with a layer of conductive material, selectively growing a second layer of insulating material over the first layer of insulating material, and opening the second layer of insulating material to the layer of conductive material while growing the second layer of insulating material.

A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

A chip includes a chip substrate having a first thickness and including a back surface. The back surface includes an etched portion with an etching depth that is less than the first thickness. The chip further includes a first thin film including a dielectric material and located on the back surface. The chip further includes a second thin film including a barrier layer material and located on the first thin film. The chip further includes a third thin film including a metal material, embedded in the chip substrate, and located on the second thin film. The chip further includes a coverage layer including nitride or carbon nitride and located on the first thin film, the second thin film, and the third thin film.

A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

Embodiments of the disclosure include apparatus and methods for molybdenum nucleation layer formation. A molybdenum nucleation layer is formed on a metal layer disposed within a damascene structure formed in a surface of a substrate maintained at a processing temperature of less than 425 degrees Celsius. The damascene structure includes a plurality of vias and the metal layer is disposed at a bottom surface of the plurality of vias. To form the molybdenum nucleation layer, a molybdenum-containing precursor (MCP) is delivered to the substrate for a first period of time. A reactive precursor gas is delivered to the substrate for the first period of time. A carrier gas is delivered to the substrate for a second period of time. The reactive precursor gas is delivered to the substrate for a third period of time. A molybdenum layer is deposited within the plurality of vias on the molybdenum nucleation layer.

Feature fill processes including deposition-inhibition-deposition operations use a boron-containing compound treatment to tune an inhibition profile. In some embodiments, a feature is non-conformally treated with a boron-containing compound such as diborane (B.sub.2H.sub.6) prior to an inhibition treatment. Treating the features with a boron-containing chemistry increases the inhibition effect of the subsequently applied inhibition treatment. The diffusion of diborane is easier to control than the diffusion of an inhibition gas such as nitrogen trifluoride (NF.sub.3), facilitating control of the inhibition profile.

Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

Methods and apparatus for transient protection of a sensitive surface of a substrate are described. Methods that facilitate transient protection of a sensitive surface of substrate include depositing a sacrificial capping layer on a sensitive surface of the substrate after a processing operation. The capping layer deposition and the prior processing operation occur under vacuum. In some embodiments, for example, the capping layer deposition and the prior processing operation occur in different modules of a tool connected by a vacuum transfer chamber. In other embodiments, the capping layer deposition and the prior processing operation occur in the same module Methods that facilitate transient protection of a sensitive surface of substrate include removing the capping layer from the sensitive surface of the substrate prior to a subsequent processing operation. The removal is performed without damaging the sensitive surface or underlying layers of the semiconductor substrate.