A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

A package structure includes forming a semiconductor substrate for RF application, a first ultra thick metal disposed over the semiconductor substrate, a second ultra thick metal disposed over the first ultra thick metal, and a bump structure directed formed on the second ultra thick metal. The second ultra thick metal is coupled to the first ultra thick metal. A patterned ground shield (PGS) structure may be formed over the semiconductor substrate and below the first ultra thick metal.