Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.

A semiconductor package includes a plurality of first semiconductor dies, a plurality of first bonding pads, a bridge layer, a plurality of second bonding pads and a plurality of second semiconductor dies. The first bonding pads are disposed on the first semiconductor dies. The bridge layer is disposed on the first bonding pads, wherein the bridge layer is electrically connected to the first semiconductor dies through the first bonding pads. The second bonding pads are disposed on the bridge layer, wherein the second bonding pads are electrically connected to the first bonding pads through the bridge layer. The second semiconductor dies are disposed on and electrically connected to the second bonding pads, wherein an active surface of the first semiconductor dies is facing an active surface of the second semiconductor dies.

An upper semiconductor build has an upper build dielectric; at least two upper build electrical signal contact bonding pads; at least one upper build dummy contact bonding pad; an upper build ground network electrically coupled to the at least two upper build electrical signal contact bonding pads; and an upper build anti-fuse dielectric between the upper build ground network and the upper build dummy contact bonding pad. A lower semiconductor build has a lower build dielectric; at least two lower build electrical signal contact bonding pads; at least one lower build dummy contact bonding pad; a lower build ground network; and a lower build anti-fuse dielectric between the lower build ground network and the lower build dummy contact bonding pad. The two builds are hybrid bonded to each other. When excess charge builds up, the anti-fuse dielectrics are blown and conduct the excess charge to ground.

A semiconductor package may include a package substrate, an interposer on the package substrate, photonics modules in the interposer and configured to perform communication based on optical signals, and a semiconductor chip on the interposer. A core substrate of the interposer may include through electrodes and cavities, where the through electrodes may extend from an upper surface of the core substrate to a lower surface of the core substrate. The cavities may extend from the upper surface of the core substrate to an inner portion of the core substrate where the through electrodes are not disposed. One of the photonics modules may be in each of the cavities. Each photonics module may include a photonics integrated circuit chip, and an electronic integrated circuit chip and an optical transmissive layer on an upper surface of the photonics integrated circuit chip.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first diffusion layer region and a second diffusion layer region; a first gate insulating film and including a portion between the first diffusion layer region and the second diffusion layer region; and a first gate electrode positioned over the first gate insulating film. The second transistor includes: a third diffusion layer region and a fourth diffusion layer region; a second gate insulating film and including a portion between the third diffusion layer region and the fourth diffusion layer region; and a second gate electrode positioned over the second gate insulating film. At least one of the first transistor or the second transistor is formed in a recess portion that has a bottom surface at a position lower than an upper surface of the device isolation portion.

A semiconductor memory device comprises: memory layers; a via wiring; a first wiring provided on one side with respect to memory layers; and an insulating layer provided on the other side with respect to memory layers, and covering an end portion of the via wiring. Memory layers each comprise: a semiconductor layer connected to the via wiring; a gate electrode facing the semiconductor layer; a second wiring connected to the gate electrode; and a memory portion connected to the semiconductor layer. The via wiring comprises: a conductive member; and an inner region having its outer peripheral surface surrounded by the conductive member. An end portion on an insulating layer side of the inner region is not covered by the conductive member, but is covered by the insulating layer, or is continuous with the insulating layer.

A semiconductor package method includes: providing a first carrier board, forming a first molding layer covering the upper surface of the first carrier board and the bridge chip after bonding an upper insulation layer of the bridge chip on the upper surface of the first carrier board; thinning the first molding layer and the lower insulation layer, and forming a first redistribution layer on the surfaces of the thinned first molding layer and lower insulation layer, the process for forming the first redistribution layer includes an electroplating process; thinning the upper insulation layer and the first molding layer, forming a second redistribution layer on the surfaces of the thinned upper insulation layer and first molding layer, and the process for forming the second redistribution layer includes an electroplating process; and providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the second redistribution layer, and the semiconductor chip being electrically connected with the second redistribution layer.

A device and method of manufacturing a semiconductor device with integrated photonic and electronic components is described. The method may include: providing a silicon-on-insulator (SOI) wafer having a silicon handle wafer, a buried oxide (BOX) layer, and a silicon waveguide layer; forming a photonic integrated circuit (PIC) including one or more of the waveguide or a metal layer; removing the silicon wafer to expose the BOX layer; and extending the BOX layer by one or more of: depositing oxide and planarizing onto the BOX layer to increase BOX layer thickness to an extended BOX layer, or fusion bonding a second wafer with a surface oxide layer. The device may include a photonic integrated circuit (PIC), an additional oxide layer, and an integrated optical component positioned to reflect or reshape optical signals within a waveguide layer vertically.

A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip, and having widths narrower than a width of the first semiconductor chip, and a molded layer on an upper surface of the first semiconductor chip. The first semiconductor chip includes first front-surface pads, a first back-surface insulating layer divided into a first region and a second region, first back-surface pads in the first region, dummy pads in the second region, the dummy pads respectively having an upper surface on which a metal oxide film is disposed, and a first through-electrode electrically connecting the first front-surface pads and the first back-surface pads to each other. The plurality of second semiconductor chips respectively includes second front-surface pads, second back-surface pads, and a second through-electrode electrically connecting the second front-surface pads and the second back-surface pads to each other.

An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.