A semiconductor package includes a wiring structure. A buffer die is disposed on the wiring structure. A logic die is disposed alongside the buffer die on the wiring structure. A first encapsulating material covers at least a portion of each of the buffer die and the logic die. A memory stack is disposed on the buffer die and is electrically connected to the buffer die. A bridge die is disposed so as to extend over at least a portion of each of the buffer die and the logic die, and is electrically connected to each of the buffer die and the logic die. A second encapsulating material covers at least a portion of each of the memory stack and the bridge die. The buffer die and the logic die are disposed at a level that is between those of the wiring structure and the bridge die.

A semiconductor device with a two-sided redistribution layer is disclosed. The semiconductor device comprises a host device and one or more memory stack cubes. A redistribution layer is disposed between and couples the host device and the memory stack cubes. This redistribution layer features an edge surface extending between the host device and the memory stack cubes. The semiconductor device includes first connective circuitry that extends through the redistribution layer, is coupled with the host device, and is exposed at the edge surface of the redistribution layer. Additionally, second connective circuitry extends through the redistribution layer, is coupled with the memory stack cubes, and is exposed at the edge surface of the redistribution layer. Connective structures couple the first and second connective circuitry exposed at the edge surface of the redistribution layer.

Methods, systems, and devices for a stacked semiconductor system are described. The stacked semiconductor system may include a semiconductor die on a redistribution layer (RDL) and a polymer material at least partially surrounding the semiconductor die. A silicon nitride material may be above the semiconductor die and on the polymer material. A logic die may be hybrid bonded with a bonding material on the silicon nitride material. And a conductive post may extend at least partially through the silicon nitride material and the polymer material and may couple the logic die with the RDL.

A method of forming a semiconductor device includes: forming a conductive pad over and electrically coupled to an interconnect structure, where the interconnect structure is disposed over a substrate and electrically coupled to electrical components formed on the substrate; forming a passivation layer over the conductive pad and the interconnect structure; and forming a sacrificial test structure over the passivation layer and electrically coupled to the conductive pad, where the sacrificial test structure includes a sacrificial pad extending along an upper surface of the passivation layer distal from the substrate, and includes a sacrificial via extending into the passivation layer and contacting the conductive pad.

A display apparatus includes a first substrate including a display area and a non-display area at least partially surrounding the display area, and a groove that overlaps the non-display area and is recessed in a thickness direction, pixels located on the first substrate and overlapping the display area, a driving chip located in the groove, and a printed circuit board located in the non-display area and overlapping the driving chip in a plan view.

A structure is disclosed. The structure can include a first processor die, a second processor die, a first memory unit, and a connecting element. The second processor die can be laterally spaced from the first processor die. The first memory unit can be disposed vertically above the first processor die. The connecting element can be disposed vertically to the first processor die and the second processor die. The connecting element can include a conductor electrically connecting the first processor die and the second processor die.

Methods, systems, and devices for polymer material gap-fill for hybrid bonding in a stacked semiconductor system are described. A stacked semiconductor may include a first semiconductor die on a semiconductor wafer. A polymer material may be on the semiconductor wafer and may at least partially surround the first semiconductor die. A silicon nitride material may be on the first semiconductor die and on the polymer material. And a second semiconductor die may be hybrid bonded with a bonding material on the silicon nitride material.

A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed opposite the first and second device features from the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

The present disclosure as an embodiment is to provide a wiring structure including a first wiring pattern; an insulation layer covering at least a portion of the first wiring pattern; a second wiring pattern disposed on the insulation layer; a via penetrating at least a portion of the insulation layer and electrically connecting the first wiring pattern and the second wiring pattern; and a protruding pattern extending into the insulation layer and having at least a portion thereof embedded in the insulation layer, the protruding pattern disposed on the first wiring pattern and connected thereto, and positioned spaced apart from the via and surrounding at least a portion of the via on the first wiring pattern.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.