The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

This disclosure relates to the process of etching and treatment of side walls while processing microdevices. One aspect is to fill the device wall indentation with a polymer. The disclosure relates to a method and device with its structure to the process of etching and treatment of sidewalls. The methods of etching, coating, and curing are used.

A semiconductor device includes: a first substrate; a second substrate including first and second regions; a stack structure in the first region and extending from the first region into the second region, the stack structure including interlayer insulating layers and gate layers, wherein the gate layers include gate pads having a step shape in the second region; a capping insulating layer at least partially covering the stack structure; an upper insulating layer on the stack structure and the capping insulating layer; a peripheral contact structure including a plurality of through-vias contacting the second substrate and spaced apart from the gate layers, and a peripheral contact pattern on the plurality of through-vias and connecting at least a portion of the plurality of through-vias to each other; a memory vertical structure; a support vertical structure; and a gate contact plug on the gate pads to be electrically connected to the gate pads.

Various embodiments of improved process flows and methods are provided herein for etching high aspect ratio (HAR) features in carbon-containing hard mask layers. In the disclosed embodiments, the improved process flows and methods combine sidewall passivation and mask de-clogging steps in a single plasma process step to improve throughput when etching HAR features (such as vias, contact holes, trenches, etc.) within a carbon-containing hard mask layer. In doing so, the improved process flows and methods disclosed herein protect the sidewall surfaces of the carbon-containing hard mask layer and prevent bowing during the HAR etch process, while also reducing processing time and improving throughput.

Semiconductor devices and methods of fabrication are provided. A method includes forming active regions on a substrate; forming an interconnect structure over the active regions; etching an opening through the interconnect structure, through the active regions, and into the substrate, wherein the opening is bounded by a sidewall; forming a via structure within the opening; and forming an air gap between the via structure and the sidewall.

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.