Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of dielectric materials interleaved with levels of conductive materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending in a direction from the first conductive level to the second conductive level, the second conductive level including a side wall; a conductive contact extending in the direction from the first conductive level to the second conductive level and contacting the second conductive level; a first dielectric material between the first conductive level and the conductive contact, the first dielectric material having a first dielectric constant; and a second dielectric material between the first dielectric material and the conductive contact, the second dielectric material having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant.

Methods and apparatus for transient protection of a sensitive surface of a substrate are described. Methods that facilitate transient protection of a sensitive surface of substrate include depositing a sacrificial capping layer on a sensitive surface of the substrate after a processing operation. The capping layer deposition and the prior processing operation occur under vacuum. In some embodiments, for example, the capping layer deposition and the prior processing operation occur in different modules of a tool connected by a vacuum transfer chamber. In other embodiments, the capping layer deposition and the prior processing operation occur in the same module Methods that facilitate transient protection of a sensitive surface of substrate include removing the capping layer from the sensitive surface of the substrate prior to a subsequent processing operation. The removal is performed without damaging the sensitive surface or underlying layers of the semiconductor substrate.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.

A method for manufacturing an interconnect structure includes: forming first and second etch stop layers respectively on first and second lower conductive portions, the first and second etch stop layers having different configurations; forming a dielectric layer to cover the first and second etch stop layers; performing a first etching process to form a first hole and a second hole in the dielectric layer to expose at least one of the first and second etch stop layers; performing a second etching process to form a first opening extending downwardly from the first hole and through the first etch stop layer, and to form a second opening extending downwardly from the second hole and through the second etch stop layer; and forming a first upper conductive portion in the first hole and the first opening, and forming a second upper conductive portion in the second hole and the second opening.

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

A method of making a semiconductor structure includes defining a first recess in an insulation layer. The method further includes forming a protection layer along a sidewall of the first recess. The method further includes forming a first conductive line in the first recess and in direct contact with the protection layer. The method further includes depositing a first insulation material over the first conductive line. The method further includes defining a second recess in the first insulation material. The method further includes forming a second conductive line in the second recess. The method further includes forming a via extending from the second conductive line, wherein the via directly contacts a sidewall of the protection layer.

Interconnect structures having dielectric layers with nitrogen-containing crusts and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a first interconnect opening in a first interlayer dielectric (ILD) layer that exposes an underlying conductive feature, such as a source/drain, a gate, a contact, a via, or a conductive line. The method includes nitridizing sidewalls of the first interconnect opening, which are formed by the first ILD layer, before forming a first metal contact in the first interconnect opening. The nitridizing converts a portion of the first ILD layer into a nitrogen-containing crust. The first metal contact can include a metal plug and dielectric spacers between the metal plug and the nitrogen-containing crust of the first ILD layer. The method can include forming a second interconnect opening in a second ILD layer that exposes the first metal contact and forming a second metal contact in the second interconnect opening.

The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature, and a contact via structure. The conductive feature is over the substrate. The contact via structure is electrically coupled to the conductive feature and includes a curved concave profile throughout a height of the contact via structure and an upper width wider than the width of the conductive feature.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.

A method includes forming a metal fill material on at least one electrical connection formed in a feature formed within a dielectric layer of a semiconductor device structure. The metal fill material partially fills the feature, the partially filled feature comprises the metal fill material and an exposed first portion of a sidewall of the feature that comprises the material of the dielectric layer, and a gap region formed between a second portion of the sidewall and a sidewall of the metal fill material, and performing a soaking process on the semiconductor device structure to form a passivation layer over a surface of the metal fill material and including a portion of the metal fill material disposed within the gap.