The present invention relates to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to an embodiment can achieve low hardness by comprising a polishing layer formed using a curing agent of specific components. It is possible to enhance the mechanical properties of the polishing pad, as well as to improve the surface defects appearing on the surface of a semiconductor substrate, by controlling the surface roughness reduction rate and the recovery elasticity index of the polishing pad to specific ranges. It is also possible to further enhance the polishing rate.

Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.

A method for processing a wafer is provided. The method includes providing a wafer, in which the wafer has a first region and a second region, and the second region is between an edge of the wafer and the first region; depositing a first metallic layer on the wafer; depositing a cap layer on the first metallic layer; disposing a dielectric layer on the cap layer, in which the dielectric layer covers a sidewall of the first metallic layer and a sidewall of the cap layer; performing a polishing process to the dielectric layer, such that a consumed portion of the cap layer and a consumed portion of the first metallic layer is formed in the second region of the wafer.

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

A composition for semiconductor processing includes abrasive particles, and a dishing control additive, comprising a first dishing control additive and a second dishing control additive. The first dishing control additive includes a compound having a betaine group and a salicylic group or a derivative thereof, and the second dishing control additive includes an azole-based compound. The first dishing control additive includes 0.07 parts by weight or more based on 100 parts by weight of the abrasive particles, and the second dishing control additive includes 0.13 parts by weight or less based on 100 parts by weight of the abrasive particles.

A slurry containing: abrasive grains; a compound X having 3 or more carbon atoms; and water, in which the abrasive grains contain cerium oxide, and a dispersion term dD in Hansen solubility parameters of the compound X is 18.0 MPa.sup.1/2 or less. A polishing method including polishing a surface to be polished by using this slurry.

A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and a conductive feature disposed in the ILD layer and electrically coupled to the first epitaxial S/D feature and the second epitaxial S/D feature. The conductive feature includes first portions having bottom surfaces contacting the first and the second epitaxial S/D features, and a second portion having a bottom surface contacting the ILD layer. The bottom surface of the second portion is above the bottom surface of the first portions.

A chemical mechanical polishing method includes transferring a substrate onto a chuck supported by a drive shaft when the chuck is located at a first height, raising the chuck to a second height greater than the first height such that a top surface of the substrate is in contact with at least one polishing pad, polishing the substate by the at least one polishing pad, lowering, the chuck to a third height lower than the second height, and transferring the substrate off of the chuck.

Embodiments of present invention provide a semiconductor structure. The structure includes a metal via having a substantially hyperboloid exterior shape; and a dielectric layer surrounding the metal via, where the metal via includes a bottom portion and a top portion; the top portion includes an outer liner and an inner liner at sidewalls thereof; and the bottom portion is directly surrounded by the dielectric layer. A method of forming the same is also provided.

The present invention provides a method for forming self-transformed support plates in shallow trench isolation for advanced semiconductor devices, in which after a photolithography process to define active areas on a silicon substrate, an additional photomask is implemented to add a support plate patterning layer in areas where silicon will be etched during a STI etching step to form STI trenches. Tiny silicon support plates inside the STI trenches are formed after the silicon etching. These silicon support plates may provide mechanical support to hold neighboring patterned strips where the active areas are defined or neighboring active areas islands, and preventing them from bending, deformed or shifting. An alignment of photomask pattern at following photolithography process is eased.