A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Examples are disclosed that relate to planarizing substrates without use of an abrasive. One example provides a method of chemically planarizing a substrate, the method comprising introducing an abrasive-free planarization solution onto a porous pad, contacting the substrate with the porous pad while moving the porous pad and substrate relative to one another such that higher portions of the substrate contact the porous pad and lower portions of the substrate do not contact the porous pad, and removing material from the higher portions of the substrate via contact with the porous pad to reduce a height of the higher portions of the substrate relative to the lower portions of the substrate. In some examples, linear motion may be used for chemically planarizing.

A semiconductor chip includes a semiconductor substrate that includes a front side and a back side that are opposite to each other, a circuit structure disposed on the front side of the semiconductor substrate, a first through via that penetrates the semiconductor substrate in a vertical direction perpendicular to the front side of the semiconductor substrate and is electrically connected to the circuit structure, and a dummy via buried in the semiconductor substrate, wherein a lower end of the dummy via is spaced apart from the back side of the semiconductor substrate.

A method of manufacturing a memory device at least includes the following steps. A first interconnect and a first dielectric layer are formed on a substrate. A first chemical mechanical polishing process is performed on the first dielectric layer. A stack structure is formed over the first dielectric layer and a staircase structure is formed in the stack structure. A second dielectric layer is formed on the substrate to cover the stack structure and the staircase structure. A second chemical mechanical polishing process is performed on the second dielectric layer. A depth of second grooves of a second polishing pad used in the second chemical mechanical polishing process is smaller than a depth of first grooves of a first polishing pad used in the first chemical mechanical polishing process. The memory device may be a 3D NAND flash memory with high capacity and high performance.

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.

The formation method of the semiconductor structure comprises: providing a substrate structure having a first trench; wherein the substrate structure comprises a base layer, an epitaxial layer, a first oxide layer, a hard mask layer and a second oxide layer arranged in sequence; the first trench penetrates through the first oxide layer, the hard mask layer and the second oxide layer, and a bottom of the first trench is located on the epitaxial layer; performing two etch-back processes on the hard mask layer of the substrate structure having the first trench and forming an isolation oxide layer on a surface of the first trench based on a thermal oxidation process between the two etch-back processes on the hard mask layer; forming an interlayer dielectric layer in the first trench to obtain a target semiconductor structure.

A method includes providing an IC package having a lead and a die encapsulated in a mold compound. The mold compound extends from a top mold surface to a base mold surface of the IC package. The method also includes trenching the mold compound from the top mold surface to the lead to form a trench. The method further includes forming a vertical wettable flank by filling the trench with a conductive material.

Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.