A stacked semiconductor device and methods for producing the same are disclosed here. A semiconductor device can include a first semiconductor die having a first backside passivation layer and a second semiconductor die having a second backside passivation layer. The first backside passivation layer interfaces to the second backside passivation layer to form a stacked semiconductor assembly and provide one or more communicative couplings between the first and second semiconductor dies. A method of forming a stacked semiconductor assembly includes aligning a first plurality of pads disposed in a first backside passivation layer of a first semiconductor die with a second plurality of pads disposed in a second backside passivation layer of a second semiconductor die. The method further includes bonding the first backside passivation layer to the second backside passivation layer to communicatively couple the first plurality of pads to the second plurality of pads.

A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a first wafer structure and at least one die stack layer stacked on a second side of the first wafer structure. The die stack has first test pad and second test pad, which can be used to test and screen the die in the die stack and the die stack, contributing to increased yield of the semiconductor device. Additionally, metal pad may be formed on a first side of the first wafer structure before the die stack is stacked on the first wafer structure, avoiding warpage or other distortion possibly otherwise caused by high-temperature treatment if they are formed after the die stack is stacked. This facilitates stacking of more dies and/or wafers together. The semiconductor device is obtainable according to the method.

Semiconductor devices having integrated cooling systems, and associated systems and methods, are disclosed herein. An example of a semiconductor device according to the present technology is a system-in-package device that includes a base substrate, a processing device and a high-bandwidth memory device that are each integrated with the base substrate, and a package cooling device that is thermally coupled to the processing device and the high-bandwidth memory device. In some embodiments, the package cooling device includes a first heat spreader thermally coupled to an upper surface of the processing device, a second heat spreader thermally coupled to an upper surface of the high-bandwidth memory device, a thermoelectric cooling device positioned between and thermally coupled to a portion of the first heat spreader and the second heat spreader, and a heat exchanger thermally coupled to the first heat spreader.

A semiconductor package may include a base chip, at least one chip stack module on the base chip, and a sealant on the base chip and sealing the at least one chip stack module. The at least one chip stack module may have an integral structure, in which a plurality of memory chips may be stacked and uniform. Each chip stack module of the at least one chip stack module may be on the base chip while having the integral structure.

A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

According to one aspect, a semiconductor package structure is provided. The semiconductor package structure includes: a plurality of first semiconductor chips arranged as being stacked along a first direction, the first semiconductor chip includes at least one first conductive structure, the first conductive structure includes a first connection structure extending along the first direction, a second connection structure extending along the first direction, and an interconnection structure between the first connection structure and the second connection structure in the first direction, and the interconnection structure is connected with both the first connection structure and the second connection structure; and a first bump connection layer between two adjacent ones of the first semiconductor chips in the first direction, the first bump connection layer includes at least one first bump structure, and the first bump structure is coupled with each of the first conductive structures in the two adjacent first semiconductor chips.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.

Methods, systems, and devices for polymer material gap-fill for hybrid bonding in a stacked semiconductor system are described. A stacked semiconductor may include a first semiconductor die on a semiconductor wafer. A polymer material may be on the semiconductor wafer and may at least partially surround the first semiconductor die. A silicon nitride material may be on the first semiconductor die and on the polymer material. And a second semiconductor die may be hybrid bonded with a bonding material on the silicon nitride material.

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.