An apparatus, comprising an interposer; a memory module, comprising a plurality of memory chips, and mounted to the interposer; and a heatsink, fastened to the interposer and configured to compress the interposer against the memory module.

An apparatus, comprising an interposer; a memory module, comprising a plurality of memory chips, and mounted to the interposer; and a heatsink, fastened to the interposer and configured to compress the interposer against the memory module.

A semiconductor device, including: a heat dissipation plate having a heat dissipation surface; a cooling module having a cooling surface, the cooling module being disposed so that the cooling surface faces the heat dissipation surface of the heat dissipation plate; and a bonding member provided between the heat dissipation surface and the cooling surface. The bonding member includes: a thermally conductive part that bonds the heat dissipation surface and the cooling surface, and an electrically conductive part that electrically connects the heat dissipation surface and the cooling surface.

A semiconductor device, including: a heat dissipation plate having a heat dissipation surface; a cooling module having a cooling surface, the cooling module being disposed so that the cooling surface faces the heat dissipation surface of the heat dissipation plate; and a bonding member provided between the heat dissipation surface and the cooling surface. The bonding member includes: a thermally conductive part that bonds the heat dissipation surface and the cooling surface, and an electrically conductive part that electrically connects the heat dissipation surface and the cooling surface.

Copper posts 22 are provided on a carrier substrate 20, and a semiconductor die 40 serving as a bridge die is attached between the copper posts 22. The semiconductor die 40 is attached by the resin layer 43 covering the terminal electrodes 42 such that the terminal electrodes 42 face the carrier substrate 20. The resin layer 43 is cured to form an encapsulant layer 23. A wiring layer 24 is formed on one side of the encapsulant layer 23, and a wiring layer 28 is formed on the other surface. Active dies 50 and 55 are attached to an interposer P. According to this method, a bridge die is attached in a face-down manner. Thus, reliable attachment can be realized. Since an expensive active die is attached last, manufacturing cost can be reduced. For the resin layer 43, an NCF or a DAF is preferably used.

A semiconductor device, including: a first circuit board, which includes: a first insulating plate, a first conductive plate embedded in the first insulating plate, the first conductive plate including a first front surface and a first back surface that are exposed from the first insulating plate, and a second conductive plate embedded in the first insulating plate, the second conductive plate including a second front surface and a second back surface that are exposed from the first insulating plate, the second conductive plate being separated from the first conductive plate; a second circuit board including a second insulating plate on which a conductive pattern layer is laid; and a semiconductor chip group including a first semiconductor chip and a second semiconductor chip, the semiconductor chip group being sandwiched between the first circuit board and the second circuit board.

A semiconductor device, including: a first circuit board, which includes: a first insulating plate, a first conductive plate embedded in the first insulating plate, the first conductive plate including a first front surface and a first back surface that are exposed from the first insulating plate, and a second conductive plate embedded in the first insulating plate, the second conductive plate including a second front surface and a second back surface that are exposed from the first insulating plate, the second conductive plate being separated from the first conductive plate; a second circuit board including a second insulating plate on which a conductive pattern layer is laid; and a semiconductor chip group including a first semiconductor chip and a second semiconductor chip, the semiconductor chip group being sandwiched between the first circuit board and the second circuit board.

A power semiconductor device, including: a power semiconductor element mounted on a principal surface of an insulating circuit substrate; a wiring substrate facing the principal surface, and including a plurality of wiring pattern layers each electrically connected to the power semiconductor element or the insulating circuit substrate; a plurality of terminals electrically connected to the power semiconductor element, each terminal having a first end and a second end; an encapsulating resin encapsulating the power semiconductor element, the insulating circuit substrate, the wiring substrate, and the second ends of the terminals with the first ends thereof exposed; and a plurality of resin holders each disposed around an outer periphery of a part of one of the terminals, and having a lower surface in contact with the wiring substrate. The terminals are all directly connected to the wiring substrate, and are all electrically connected to the plurality of wiring pattern layers.

A power semiconductor device, including: a power semiconductor element mounted on a principal surface of an insulating circuit substrate; a wiring substrate facing the principal surface, and including a plurality of wiring pattern layers each electrically connected to the power semiconductor element or the insulating circuit substrate; a plurality of terminals electrically connected to the power semiconductor element, each terminal having a first end and a second end; an encapsulating resin encapsulating the power semiconductor element, the insulating circuit substrate, the wiring substrate, and the second ends of the terminals with the first ends thereof exposed; and a plurality of resin holders each disposed around an outer periphery of a part of one of the terminals, and having a lower surface in contact with the wiring substrate. The terminals are all directly connected to the wiring substrate, and are all electrically connected to the plurality of wiring pattern layers.

An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.