A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.

A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die, a package substrate, and at least one bonding wire. The package substrate includes a dam structure to define a space where the semiconductor die is placed. The bonding wire is electrically connected between the semiconductor die and the package substrate.

A semiconductor package including a package substrate; an intermediate substrate on the package substrate; an optical engine unit on the intermediate substrate; a logic device adjacent to the optical engine unit and on the intermediate substrate; and a memory device adjacent to the logic device and on the intermediate substrate, wherein the optical engine unit includes a first redistribution substrate, a photonic integrated circuit (PIC) chip on the first redistribution substrate, an electronic integrated circuit (EIC) chip on the PIC chip, a multi-insulating layer surrounding the PIC chip and the EIC chip, and a transparent support layer on the EIC chip and the multi-insulating layer.

A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

A semiconductor package includes a first chip structure on a first substrate and a first molding layer surrounding the first chip structure on the first substrate, wherein the first chip structure includes a first chip including a PIC on the first substrate, a second chip including an EIC on the first chip, a transparent layer horizontally spaced from the second chip on the first chip, a microlens layer on the transparent layer; and a second molding layer surrounding the second chip, the transparent layer, and the microlens layer on the first chip, the semiconductor package further includes a first insulating layer on an upper surface of the first chip and a second insulating layer on a lower surface of the transparent layer, and the first and second 10 insulating layers are in contact with each other, and the first and second insulating layers are integrally formed of the same material.

A semiconductor package may include an interposer substrate having first and second surfaces, a through electrode extending through the interposer substrate, an RDL on the first surface of the interposer substrate and an upper surface of the through electrode and including a redistribution wiring structure, first and second semiconductor chips electrically connected to the redistribution wiring structure on the RDL, a first molding member on the RDL and covering sidewalls of the first and second semiconductor chips, a conductive post on the second surface of the interposer substrate and contacting the through electrode, and a second molding member on the second surface of the interposer substrate and covering a sidewall of the conductive post. A maximum width of the through electrode is equal to or greater than that of the conductive post. A length of the through electrode is equal to or less than that of the conductive post.

An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.