In a semiconductor device, a first wiring member is electrically connected to a first main electrode on a first surface of a semiconductor element, and a second wiring member is electrically connected to a second main electrode on a second surface of the semiconductor element. An encapsulating body encapsulates at least a part of each of the first and second wiring members, the semiconductor element and a bonding wire. The semiconductor element has a protective film on the first surface of the semiconductor substrate, and the pad has an exposed surface exposed from an opening of the protective film. The exposed surface includes a connection area to which the bonding wire is connected, and a peripheral area on a periphery of the connection area. The peripheral area has a surface that defines an angle of 90 degrees or less relative to a surface of the connection area.

In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.

Aspects of the present disclosure include systems, structures, circuits, and methods providing voltage-isolated integrated circuit (IC) packages or modules having a transformer integrated with or implemented on a lead frame. A portion of transformer windings may include a conductive portion of a lead frame. Conductive structure, such as wire bonds, may be used for other portions of transformer windings. In some examples, an insulating coating may be placed on the package to increase the isolation capability of the final package. The IC packages and modules may include various types of circuits; in some examples, IC packages or modules may include a galvanically isolated gate driver or other high voltage circuit.

A method of forming a semiconductor device includes forming a base leadframe having a plurality of leads and a die pad. A cavity is formed in each lead of a set of leads of the plurality of leads. Bond pads of a first semiconductor die are interconnected with respective leads of the plurality of leads. A metal core connector is placed on each cavity of the set of leads. A packaged device is mounted on the base leadframe by way of the metal core connectors. The packaged device includes a second semiconductor die mounted on package leads of a package leadframe. A first encapsulant encapsulates the second semiconductor die and package leadframe. A portion of each of the package leads is exposed through the first encapsulant. A second encapsulant encapsulates the first semiconductor die, a portion of the base leadframe, and a portion of the packaged device.

A packaging structure and a manufacturing method thereof are provided. The packaging structure includes a substrate, a plurality of antenna module assembly, a first encapsulant layer, a superstrate, and a radome. The plurality of antenna module assembly is arranged in an array over the substrate. The first encapsulant layer is disposed on the array of antenna module assemblies and encapsulates each of the array of antenna module assemblies. The superstrate is disposed on the first encapsulant layer. An orthographic projection area of the superstrate on the substrate is larger than an orthographic projection area of each of plurality of antenna module assembly on the substrate. The radome is disposed on the superstrate.

The present disclosure provides a semiconductor package. The semiconductor package includes a substrate, a die, a thermally conductive material, a plurality of bonding wires, a molding compound, and a heat-dissipating frame. The substrate has opposing top and bottom surfaces. The thermally conductive material is disposed between the die and the substrate to bond the die to the top surface of the substrate. One end of each of the bonding wires is connected to the die and the other end of each of the bonding wires is connected to the top surface of the substrate. The molding compound is formed on the top surface of the substrate to cover the die and the bonding wires. The heat-dissipating frame is disposed on the top surface of the substrate to enclose the molding compound. The present disclosure further provides a method of manufacturing the above semiconductor package.

A semiconductor package including a printed circuit board, a plurality of semiconductor chips arranged apart from the printed circuit board in a vertical direction and a plurality of bonding wires. Each of the bonding wires including a first end in contact with the printed circuit board, and a second end in contact with a chip pad included in each of the plurality of semiconductor chips. The semiconductor package further including a first encapsulation layer filling spaces between lower surfaces of the plurality of semiconductor chips and an upper surface of the printed circuit board and spaces between the plurality of bonding wires, and a second encapsulation layer covering an upper surface of the first encapsulation layer and the plurality of semiconductor chips and including a flat upper surface arranged apart from the upper surface of the printed circuit board by a same height in all areas.

Provided is a semiconductor chip including a semiconductor chip including a semiconductor substrate including a first surface and a second surface opposite to the first surface, a wiring layer arranged on the first surface of the semiconductor substrate, a plurality of through electrodes extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, a plurality of chip pads arranged on the second surface of the semiconductor substrate and electrically connected to the plurality of through electrodes, and a passivation layer arranged on the second surface of the semiconductor substrate and in contact with side surfaces of the plurality of chip pads. The passivation layer includes an insulating layer and an oxide layer arranged on the insulating layer. The insulating layer includes an insulating pattern having a first width along a horizontal direction. The oxide layer includes a first oxide pattern having a second width along the horizontal direction. The first width is greater than the second width.

A semiconductor device and a method of forming a semiconductor device are provided. The semiconductor device includes a first die, a diamond layer and an encapsulant. The diamond layer is disposed on the first die. The encapsulant is disposed on the first die, wherein the encapsulant encapsulates the diamond layer.

Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.