According to one aspect of the present disclosure, a memory apparatus is provided. The memory apparatus may include a first memory die and a die group stacked in a first direction. The die group may include M second memory dies stacked in the first direction. Each of the second memory dies may be connected to a third memory die and configured to perform data exchange at a bandwidth of (N*X) bits with the third memory die through N data channels. The first memory die may be connected to the third memory die. The first memory die may be configured to perform data exchange at a bandwidth of (N*X) bits with the third memory die through N data channels. The first memory die may be configured to replace a first data channel of the die group when a storage portion corresponding to the first data channel fails.

A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, a second semiconductor die, a first thermal interface material (TIM) film, a second TIM film, and a heat-dissipating lid. The redistribution layer is attached to the substrate. The first semiconductor die and the second semiconductor die are disposed over the redistribution layer. The first TIM film is formed over the first semiconductor die. The second TIM film is formed over the second semiconductor die. The heat-dissipating lid is attached to the substrate. The heat-dissipating lid has first regions with a first cavity depth and a second region with a second cavity depth. The second cavity depth is greater than the first cavity depth. The second TIM film is disposed in the second region of the heat-dissipating lid.

A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

A semiconductor package may include: a first double-chip structure including a first semiconductor chip, a second semiconductor chip, a first scribe lane region dividing the first semiconductor chip and the second semiconductor chip, and a first through hole in the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure including a third semiconductor chip, a fourth semiconductor chip, a second scribe lane region dividing the third semiconductor chip and the fourth semiconductor chip, and a second through hole in the second scribe lane region; first conductive connection members between the first and second double-chip structures and configured to electrically connect the first and third semiconductor chips and the second and fourth semiconductor chips; and a molding member on the first double-chip structure and the second double-chip structure and in the first through hole and the second through hole.

A 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes vertical interconnects to provide interconnections between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first package die and a second die contact on the second side of the first package die. The second package die couples to the second die contacts of the first package die to form power and/or signal interconnects between the package substrate and the second package die. Horizontal interconnects in a distribution layer on the first side of the first package die distribute power and signals horizontally between the first die contacts and the vertical interconnects.

In examples, a semiconductor package comprises a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate. The package includes a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region. The package also includes conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuity region. The package further comprises a first support member coupled to the device side of the semiconductor die and extending toward the substrate and not touching the substrate or a second support member coupled to the substrate. The package also includes a ring on the substrate and encircling the bond pads and a glob top member covering the semiconductor die and a portion of the substrate circumscribed by the ring. The package also includes a mold compound covering the glob top member and the substrate.