Patent classifications
H10W74/141
Dam structure for integrated passive device integration and methods of forming the same
An embodiment semiconductor package assembly may include an interposer, an integrated passive device electrically coupled to a first side of the interposer, an underfill material portion formed between the integrated passive device and the first side of the interposer, and a dam protruding from the first side of the interposer and configured to constrain a spatial extent of the underfill material portion. The dam may include a first portion extending above a surface of the first side of the interposer and a second portion embedded below the surface of the first side of the interposer. The dam may be formed in a dielectric layer that also includes a component of a redistribution interconnect structure. The dam may further be electrically isolated from the redistribution interconnect structure and may be configured to form a connected or disconnected boundary of a two-dimensional region of the first side of the interposer.
PACKAGING FOR SEMICONDUCTOR DEVICES FOR HIGH PERFORMANCE COMPUTING APPLICATIONS AND METHODS FOR FORMING THE SAME
A semiconductor device and methods of forming the same. In some embodiments, a method for forming a semiconductor device includes forming a redistribution layer that includes connecting vias and a surface mount pad via and the top surface width of each via is larger than a bottom surface width. The method includes connecting a component to the redistribution layer by a plurality of -bumps and filling a gap between the component and the redistribution layer with a mold and an underfill. The method includes etching back the redistribution layer to expose the surface mount pad via and attaching a surface mount pad to the surface mount pad via. The surface mount pad is connected to the bottom surface width of the surface mount pad via and the surface mount pad includes a protrude. The method includes connecting a device to a bottom surface of the surface mount pad.
SEMICONDUCTOR PACKAGE
A semiconductor package is provided. The semiconductor package comprises a first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die including a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer in contact with the first surface of the first semiconductor die; and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die, wherein a width of the first bonding layer in a horizontal direction is smaller than a width of the second bonding layer in the horizontal direction, wherein the width of the second bonding layer in the horizontal direction is greater than a width of the first semiconductor die in the horizontal direction.
PACKAGE STRUCTURE CONTAINING CHIP STRUCTURE WITH INCLINED SIDEWALLS
A package structure is provided. The package structure includes a chip structure having a first side region, a second side region, and a corner region. The chip structure has an inclined sidewall, and the first side region and the second side region meet at the corner region. In a top view, the corner region has a rounded profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction. The second side region has a second substantially straight-line profile and extends towards the corner region along a second direction. The second direction is substantially perpendicular to the first direction. The package structure also includes a protective layer laterally surrounding the chip structure.
SEMICONDUCTOR DEVICES HAVING DUMMY DIES AND METHODS OF MAKING THE SAME
Semiconductor devices having dummy dies and methods of fabricating semiconductor devices with dummy dies. An embodiment semiconductor device includes an interconnect structure and one or more active devices attached to the interconnect structure, the one or more active devices being electrically connected to the interconnect structure through a plurality of conductive bumps. The semiconductor device includes a dummy die attached to the interconnect structure by an adhesive layer, wherein the adhesive layer comprises one of a die attach film (DAF) layer, a film over wire (FOW) layer, or a non-conductive film (NCF) layer.