A semiconductor package includes an interposer structure, a first semiconductor die, semiconductor dies, a first molding layer, and an encapsulant. The first semiconductor die and the second semiconductor dies are located over and electrically coupled to the interposer structure. The second semiconductor dies are laterally disposed adjacent to the first semiconductor die that includes memory dies and at least one dummy die. The first molding layer laterally surrounds the at least one dummy die. The encapsulant is disposed on the interposer structure and encapsulates the first semiconductor die and the second semiconductor dies. The first molding layer is disposed between at least one dummy die and the encapsulant. The dimensions of the memory die are substantially equal to the total dimensions of each of the at least one dummy die and the first molding layer.

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.

Implementations of a substrate may include a semiconductor material; a redistribution layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through a thickness of the semiconductor material, the hollow via directly coupled with the redistribution layer.