A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first substrate, a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first substrate includes a cavity; the first chip is embedded in the cavity and includes a first connecting surface and a first heat-conducting surface that face away from each other; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, a side of the second chip distal from the first chip includes a second heat-conducting surface on a side; and the first heat conductor is connected to the first heat-conducting surface, and the second heat conductor is connected to the second heat-conducting surface. The first substrate includes a third connecting surface that is flush with the first connecting surface.

A semiconductor assembly, a packaging structure, and associated method for corner stress reduction in semiconductor devices. The assembly includes a plurality of semiconductor dies and a plurality of spacers. Each spacer in the plurality of spacers is disposed between and configured to separate two semiconductor dies in the plurality of semiconductor dies. At least one spacer in the plurality of spacers has at least one extended spacer corner feature configured to extend toward at least one corner of at least one semiconductor die in the plurality of semiconductor dies disposed adjacent to the at least one spacer. At least one extended spacer corner feature is configured to reduce stress on at least one semiconductor die.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

There is provided a semiconductor memory device that has improved performance and/or reliability. The semiconductor memory device includes a substrate, a stacked structure including a plurality of gate electrodes stacked on the substrate and spaced apart from each other in a first direction, the first direction being perpendicular to an upper surface of the substrate, a channel structure extending in the first direction and crossing the plurality of gate electrodes, and a dam structure extending in the first direction and surrounding at least a portion of the stacked structure in a plan view, on the substrate. A height of an upper surface of the dam structure from the upper surface of the substrate is lower than a height of the channel structure from the upper surface of the substrate.

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A method of manufacturing a semiconductor package may include: preparing a semiconductor wafer including rear pads and a rear insulating layer surrounding the rear pads, the rear insulating layer including first recesses spaced apart from the rear pads in a first lateral direction; preparing second semiconductor chips including front pads and a front insulating layer surrounding the front pads, the front insulating layer including second recesses spaced apart from the front pads in the first lateral direction; forming an air gap between the first recesses and the second recesses in a vertical direction by disposing the second semiconductor chips on the semiconductor wafer, the rear pads contacting the front pads; and bonding the rear insulating layer and the front insulating layer to each other and bonding the rear pads and the front pads to each other by performing a thermal compression process.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.