A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

A semiconductor package may include a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip in a vertical direction, adhesive layers interposed between the first semiconductor chip and one of the second semiconductor chips and between the second semiconductor chips, and a molding member on the first semiconductor chip. Edges of the adhesive layers may be positioned inward from sidewalls of the second semiconductor chips. The molding member may cover at least sidewalls of the second semiconductor chips and sidewalls of the adhesive layers. The molding member may fill edge gaps defined by the sidewalls of the adhesive layers and edges of upper surfaces and lower surfaces of the second semiconductor chips.

A semiconductor device includes a cell structure including gate electrodes and mold insulating layers alternately stacked one by one in a vertical direction, a channel structure extending in the vertical direction through the gate electrodes and the insulating layers, wherein a first end portion of the channel structure protrudes upward from an uppermost mold insulating layer, and a common source layer connected to the first end portion of the channel structure and located on the uppermost mold insulating layer. The uppermost mold insulating layer includes a first low-refractive-index layer on a lower surface of the common source layer, a high-refractive-index layer on a lower surface of the first low-refractive-index layer, and a second low-refractive-index layer on a lower surface of the high-refractive-index layer.

A method of fabricating a semiconductor device may include forming a lower mold structure on a substrate, forming a first mold structure on the lower mold structure, the first mold structure including first interlayer insulating layers and first sacrificial layers, which are alternately stacked in a vertical direction, forming first vertical channel holes to penetrate the first mold structure, the lower mold structure, and a portion of the substrate, and forming an active layer to cover a top surface of the first mold structure and extend to an upper side surface of each of the first vertical channel holes. The active layer may include a horizontal portion covering the top surface of the first mold structure and a vertical portion covering the upper side surface of each of the first vertical channel holes, and the active layer may include a metallic material.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

A semiconductor package, includes: a first semiconductor chip including first connection pads on the first front surface, and through electrodes extending perpendicularly to the first rear surface and electrically connected to at least a portion of the first connection pads; a second semiconductor chip including second connection pads on the second front surface, and on the first rear surface so that the second rear surface faces the first semiconductor chip; a dielectric layer on the second semiconductor chip; first conductive structures in the dielectric layer, and connecting the through electrodes of a first group and the second connection pads; second conductive structures in the dielectric layer, and having first and second ends, the first ends connected to the through electrodes of a second group and at least a portion of the second ends thereof being exposed from the dielectric layer; at least one third semiconductor chip including third connection pads on the third front surface, and on the dielectric layer so that the third rear surface faces the second semiconductor chip; conductive wires connecting the second conductive structures and the third connection pads.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.

An example of a semiconductor package includes a buffer die having a first planarize area, a memory die stack structure including middle core dies and a top core die stacked on the buffer die in a vertical direction and having a second planar area smaller than the first planar area, an adhesion layer contacting an upper surface of the memory die stack structure, a dummy die contacting the adhesion layer and having a third planar area greater than the first planar area, and a molding structure under the dummy die and covering sidewalls of the buffer die, the memory die stack structure and the adhesion layer.

Disclosed herein are related to a device comprising a memory chip, another memory chip, and a circuit chip between the memory chip and the another memory chip, where the circuit chip is connected to the memory chip and the another memory chip through different connections. The memory chip may include a first memory array and a first bond pad, and the another memory chip may include a second memory array and a second bond pad. The circuit chip may include a third bond pad on a first surface of the circuit chip coupled to the first bond pad, and a fourth bond pad on a second surface of the circuit chip coupled to the second bond pad. The circuit chip may include a transistor coupled to the third bond pad through a front side connection and another transistor coupled to the fourth bond pad through a backside connection.