A semiconductor memory device includes a mold structure including a plurality of gate electrodes stacked in a first direction perpendicular to a top surface of a substrate and a channel structure penetrating the mold structure, and the channel structure may include a light source configured to emit light, a light detector spaced apart from the light source in the first direction and configured to detect light, and a waveguide, through which the light emitted from the light source passes, disposed between the light source and the light detector.

A semiconductor device may include high-integrated memory cells, and a method for fabricating the semiconductor device may include forming a first mold stack and a first bonding layer on a substrate; forming a second mold stack and a second bonding layer on a sacrificial substrate; flipping the sacrificial substrate and bonding the first and second bonding layers; removing the sacrificial substrate; and forming a plurality of memory cells vertically stacked in the first and second mold stacks.

A semiconductor memory device includes a mold structure including a plurality of gate electrodes, a gate electrode cutting pattern separating the mold structure into a plurality of blocks by cutting the plurality of gate electrodes along a plane, within a first block being at least one block among the plurality of blocks, a plurality of first capacitor structures penetrating the mold structure, a plurality of second capacitor structures penetrating the mold structure within the first block, a first capacitor connection structure on the first block, and connected to the plurality of first capacitor structures, and a second capacitor connection structure on the first block, is connected to the plurality of second capacitor structures. A first signal line connected to the first capacitor connection structure and a second signal line connected to the second capacitor connection structure are electrically separated.

A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.

A package structure and a method for manufacturing the same, and an electronic device are provided. The package structure includes a substrate, a chip stack, a heat dissipation layer, and a molding layer. The chip stack is disposed on the substrate, the heat dissipation layer is disposed on the chip stack, and the molding layer is disposed on the substrate and covers the chip stack. The molding layer is in contact with the heat dissipation layer, the molding layer and the heat dissipation layer are coplanar, and the thermal conductivity coefficient of the plastic encapsulating layer is less than the thermal conductivity coefficient of the heat dissipation layer.

An electronic package technology is disclosed. A first active die can be mountable to and electrically coupleable to a package substrate. A second active die can be disposed on a top side of the first active die, the second active die being electrically coupleable to one or both of the first active die and the package substrate. At least one open space can be available on the top side of the first active die. At least a portion of a stiffener can substantially fill the at least one open space available on the top side of the first active die.

A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.

According to an embodiment, a semiconductor device includes a first chip including a substrate, and a second chip bonded to the first chip at a first surface. Each of the first chip and the second chip includes an element region, and an end region including a chip end portion. The first chip includes a plurality of first electrodes that are arranged on the first surface in the end region and are in an electrically uncoupled state. The second chip includes a plurality of second electrodes that are arranged on the first surface in the end region, are in an electrically uncoupled state, and are respectively in contact with the first electrodes.

A chip stacking structure includes: a first chip, a second chip stacked with the first chip, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first conductive channel, and a second conductive channel; the first redistribution layer is disposed on a surface of the first chip facing the second chip; the second redistribution layer is disposed on a passive surface of the second chip, and the third redistribution layer is disposed on an active surface of the second chip; the first conductive channel passes through the second chip and the third redistribution layer, connecting the first redistribution layer and the second redistribution layer; and the second conductive channel passes through the second chip, connecting the second redistribution layer and the third redistribution layer.

A semiconductor package is provided. The semiconductor package includes a first structure with a first insulating layer and a connection pad which penetrates through the first insulating layer; and a second structure with a second insulating layer bonded to the first insulating layer and a pad structure provided in a recess portion of the second insulating layer. The pad structure is bonded to and wider than the connection pad. The pad structure includes: an electrode pad disposed on a bottom surface of the recess portion; a solder disposed on the electrode pad and bonded to the connection pad; and a conductive support disposed to surround a side surface of the solder on the electrode pad and bonded to the first insulating layer. A melting point of the conductive support is higher than a melting point of the solder.