The present disclosure as an embodiment is to provide a wiring structure including a first wiring pattern; an insulation layer covering at least a portion of the first wiring pattern; a second wiring pattern disposed on the insulation layer; a via penetrating at least a portion of the insulation layer and electrically connecting the first wiring pattern and the second wiring pattern; and a protruding pattern extending into the insulation layer and having at least a portion thereof embedded in the insulation layer, the protruding pattern disposed on the first wiring pattern and connected thereto, and positioned spaced apart from the via and surrounding at least a portion of the via on the first wiring pattern.

Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and/or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1 C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds. The example techniques can direct-bond lithium tantalate LiTaO.sub.3 to various conventional substrates in a process for making various novel optical and acoustic devices.

A method of manufacturing a metal structure for an optical semiconductor device, including a treatment step (1) of immersing in and/or applying the solution containing a polyallylamine polymer a base body, the base body including an outermost layer at a portion or entire surfaces of the base body, the outermost layer including a plating of at least one selected from the group consisting of gold, silver, a gold alloy, and a silver alloy, so as to manufacture the metal structure for an optical semiconductor device having an increased adhesion to a resin material.

According to a manufacturing method of the present invention, it is possible to manufacture a busbar assembly in an efficient manner, the busbar assembly including busbars disposed in parallel in a common plane and an insulative resin layer including a gap filling portion filled into a gap between the adjacent busbars and a bottom-surface-side laminated portion extending integrally from the gap filling portion and arranged on bottom surfaces of the busbars, a top surface of the busbar being at least partially exposed to form a top-surface-side connection portion, the bottom surface of the busbar including a first bottom surface region which is located at the same position in a thickness direction as a lower end portion of the gap and on which the bottom-surface-side laminated portion is arranged and a second bottom surface region located farther away from the top surface than the first bottom surface region and exposed to the outside to form a bottom-surface-side connection portion.

This invention provides opportunity for diamond and bi-wafer microstructures to be implemented in advanced ICs and advanced IC packages to form a new breed of ICs and SiPs that go beyond the limitations of silicon at the forefront of IC advancement due primarily to diamond's extreme heat dissipating ability. Establishing the diamond and bi-wafer microstructure capabilities and implementing them in advanced ICs and advanced IC packages gives IC and package architects and designers an extra degree of design freedom in achieving extreme IC performance, particularly when thermal management presents a challenge. Diamond's extreme heat spreading ability can be used to dissipate hotspots in processors and other high-power chips such as GaN HEMT, resulting in performance and reliability enhancement for IC and package applications covering HPC, AI, photonics, 5G RF/mmWave, power and IoT, and at the system level propelling the migration from traditional computing to near-memory computing and in-memory computing.

A semiconductor device includes a dielectric interposer, a first RDL, a second RDL, and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first RDL is disposed over the first surface of the dielectric interposer. The second RDL is disposed over the second surface of the dielectric interposer. The conductive structures are disposed through the dielectric interposer and directly contact the dielectric interposer. The conductive structures are electrically connected to the first RDL and the second RDL. Each of the conductive structures has a tapered profile. A minimum width of each of the conductive structures is proximal to the first RDL, and a maximum width of each of the conductive structures is proximal to the second RDL.

This metal sheet material is made of copper or a copper alloy, and includes a main sheet body and a roughened plating layer that is formed on an outermost surface layer of the main sheet body. An engagement protrusion that protrudes toward the opposite side to the main sheet body and has a widening portion that gradually widens in width toward a tip end side in a protrusion direction is formed in the roughened plating layer. In a cross section of the main sheet body along the thickness direction, a plurality of the engagement protrusions are formed on a surface crystal grain that is located on the outermost surface of the main sheet body.

Provided is a package substrate. In a manufacturing method thereof, by combining two extremely thin substrates to be processed on opposite sides of a carrier (and/or a support member), a first circuit layer and a second circuit layer are respectively formed on opposite sides of a core layer of the substrate. Therefore, the structural thickness required for the manufacturing process is increased such that the processability of the ultra-thin substrates is not limited by the equipment performance, thereby eliminating the need for specialized equipment and significantly reducing processing costs.

A package is disclosed. In one example, the package comprises a carrier having a first main surface at which at least one first pad is formed and an opposing second main surface at which at least one second pad is formed at least partially in an electrically insulating layer structure of the carrier. An electronic component is mounted on or above the carrier, electrically connected with the at least one first pad and arranged spaced with respect to the at least one second pad by the carrier. The at least one second pad comprises a first metallic area facing the carrier and a second metallic area connected at an interface with the first metallic area and facing away from the carrier.

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of first metal wires, a plurality of second metal wires, a ring-shaped supporting layer formed on the sensor chip, and a light-permeable sheet. The first metal wires and the second metal wires are connected to the substrate and the sensor chip. Each edge of a top surface of the sensor chip is provided with at least one of the second metal wires adjacent thereto. Each of the second metal wires has a highest endpoint that is higher than a highest endpoint of any one of the first metal wires with respect to the substrate, and the light-permeable sheet is disposed on the ring-shaped supporting layer and abuts against the highest endpoints of the second metal wires, such that the first metal wires are not in contact with the light-permeable sheet.