An interconnect substrate includes a pad for external connection and an insulating layer, wherein part of a lower surface of the pad is covered with the insulating layer, wherein the pad is situated in a recess formed in an upper surface of the insulating layer, such that a groove is present between the pad and a perimeter of the recess around the pad in a plan view of the interconnect substrate, and wherein a bottom surface of the groove is coplanar with the lower surface of the pad.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

Provided is a semiconductor package including a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip, a step cover layer surrounding side surfaces of the plurality of second semiconductor chips and covering side portions of the plurality of second semiconductor chips, wherein a maximum thickness of the step cover layer is 40 micrometers (m) or less, and a moisture barrier layer covering an outer surface of the step cover layer.

Methods, systems, and devices for die side interconnect are described. A semiconductor assembly may include a stack of first dies (e.g., memory dies) coupled with a second die (e.g., a logic die) using a sideways architecture. For example, the semiconductor assembly may include multiple first dies, where a top surface of one the first dies is coupled with a bottom surface of another of the first dies to form the stack. The first dies each have a side surface coupled with an upper surface of the second die. The first dies each include a conductive via extending from the top surface of the respective first die at least partially towards the bottom surface of the respective first die. The first dies each include a redistribution layer coupled with the conductive via and extending parallel with the top surface of the respective first die.

A semiconductor device has a substrate formed on a first carrier. A semiconductor die is mounted on the substrate. An interconnect structure is formed on a second carrier. A copper pillar is formed on the substrate or interconnect structure. The interconnect structure is disposed over the substrate with the copper pillar and semiconductor die between the substrate and interconnect structure. The first carrier and second carrier are removed after disposing the interconnect structure over the substrate. A system-in-package (SiP) is mounted to the substrate opposite the semiconductor die after removing the first carrier.

A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.

A semiconductor package may include: a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; a second semiconductor chip on the interposer; and a molding layer filling a portion between the first semiconductor chip and the second semiconductor chip, wherein the interposer includes a first pillar and a second pillar, wherein the package substrate includes a first substrate pad corresponding to the first pillar, and a second substrate pad corresponding to the second pillar, wherein the package substrate includes an insulating layer on a first portion of an upper surface of the first substrate pad and on a first portion of an upper surface of the second substrate pad, and wherein the package substrate further includes a first connection terminal between the first pillar and the first substrate pad, and a second connection terminal between the second pillar and the second substrate pad.

An electronic device includes a first electronic unit, a molding layer and a circuit structure. The molding layer surrounds the first electronic unit. The circuit structure is disposed at a side of the molding layer and electrically connected to the first electronic unit. The circuit structure includes a first portion and a second portion disposed between the first portion and the first electronic unit in a normal direction of the electronic device. The first portion includes a first insulating layer, the second portion includes a second insulating layer and a third insulating layer, the second insulating layer is disposed between the first insulating layer and the third insulating layer, the third insulating layer is disposed between the second insulating layer and the molding layer, and a dielectric loss of the second insulating layer is less than dielectric losses of the first insulating layer and the third insulating layer.

A semiconductor device includes a circuit substrate, a first semiconductor element, a second semiconductor element, and a connection element. The circuit substrate includes a first pad. The first semiconductor element is disposed on the circuit substrate and includes a second pad and a third pad. The second semiconductor element is disposed on the circuit substrate. The connection element is disposed on the circuit substrate and electrically connects the first semiconductor element and the second semiconductor element. The connection element includes a fourth pad. The second pad is bonded to the first pad through a conductive material, and the third pad is directly bonded to the fourth pad.

A semiconductor package comprises a multi-layer substrate including multiple metal layers and a solid dielectric layer contacting the multiple metal layers. The multi-layer substrate includes first conductive terminals on a bottom surface of the multi-layer substrate, with the first conductive terminals coupled to the multiple metal layers. The multi-layer substrate includes second and third conductive terminals on a top surface of the multi-layer substrate opposing the bottom surface of the multi-layer substrate, the second and third conductive terminals coupled to the multiple metal layers. The package includes multiple metal members on the second conductive terminals, and a capacitor coupled to the multiple metal members, with the multiple metal members forming a gap between the capacitor and the multi-layer substrate. The package includes a semiconductor die on the top surface of the multi-layer substrate and bond wires coupled to the third conductive terminals. The package includes a mold compound.