A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.

A semiconductor package includes a first redistribution structure including a first redistribution layer; a semiconductor chip on a first surface of the first redistribution structure and including a connection pad electrically connected to the first redistribution layer; an encapsulant that surrounds at least a portion of the semiconductor chip; a second redistribution structure on the encapsulant and including a second redistribution layer; a through-via structure that extends through the encapsulant and electrically connects the first redistribution layer to the second redistribution layer; an organic material layer between the through-via structure and the encapsulant and having an elongation rate greater than an elongation rate of the encapsulant; and a bump structure on a second surface of the first redistribution structure.

A semiconductor package includes a first redistribution structure including a first redistribution layer; a semiconductor chip on a first surface of the first redistribution structure and including a connection pad electrically connected to the first redistribution layer; an encapsulant that surrounds at least a portion of the semiconductor chip; a second redistribution structure on the encapsulant and including a second redistribution layer; a through-via structure that extends through the encapsulant and electrically connects the first redistribution layer to the second redistribution layer; an organic material layer between the through-via structure and the encapsulant and having an elongation rate greater than an elongation rate of the encapsulant; and a bump structure on a second surface of the first redistribution structure.

A semiconductor package includes a package substrate including first and second interconnection layers sequentially stacked and a first semiconductor device on the package substrate. The first interconnection layer includes first and second lower insulating layers sequentially stacked and a first interconnection line on the second lower insulating layer, the second interconnection layer includes first and second inorganic insulating layers sequentially stacked and a first connection pad in the second inorganic insulating layer, and the first semiconductor device includes a third inorganic insulating layer at a bottom of the first semiconductor device and contacting the second inorganic insulating layer and a second connection pad in the third inorganic insulating layer and contacting the first connection pad. The first and second lower insulating layers are formed of different materials from the first and second inorganic insulating layers, and the first inorganic insulating layer contacts a sidewall and upper surface of the first interconnection line.

A device includes a substrate that includes a multilayer dielectric-metal structure including sidewall(s) that define an embedding region within the multilayer dielectric-metal structure. The multilayer dielectric-metal structure includes dielectric layers and metal layers patterned to define metal lines. The multilayer dielectric-metal structure also includes component(s) disposed within the embedding region. The substrate includes PID layers coupled to surfaces of the multilayer dielectric-metal structure and to surfaces of the component(s). The substrate also includes a metal structure including a portion in contact with at least one of the sidewall(s) of the multilayer dielectric-metal structure and at least one sidewall of one of the component(s), where the portion of the metal structure electrically couples a component and the metal lines of the multilayer dielectric-metal structure.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure, a first interposer, a second interposer, a first semiconductor die, and a second semiconductor die. The substrate structure has a first surface and a second surface opposite to the first surface. The first interposer is disposed over the first surface of the substrate structure. The second interposer is disposed over the first interposer. The first and the second semiconductor dies are disposed over the first surface of the substrate structure, and the first and the second semiconductor dies are bonded to two opposite sides of the second interposer, respectively. The substrate structure includes a thermal enhancement portion, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure.

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first electronic component, and an electronic device. The first electronic component is disposed over the substrate. The electronic device is at least partially embedded in the substrate. The electronic device includes a second electronic component and a reinforcement. The second electronic component is configured for providing a regulated voltage to the first electronic component. The reinforcement supports the second electronic component.

A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.

A method includes: forming an interposer die using a substrate, the interposer die including a plurality of conductive vias in the substrate; bonding the interposer die to a first redistribution layer (RDL); encapsulating the interposer die; forming a second RDL over the interposer die on a side opposite to the first RDL; bonding a first semiconductor die with one of the first RDL and the second RDL; and encapsulating the first semiconductor die.

A packaging substrate according to the present disclosure comprises a core layer; a first conductive layer, which is a conductive layer disposed in contact with an upper surface of the core layer; and an adhesion reinforcement layer disposed on the core layer and surrounding at least a portion of the first conductive layer. The adhesion reinforcement layer comprises any one selected from the group consisting of a silicon-based compound, an acrylic-based compound, and a combination thereof. An arithmetic average roughness (Ra) value of the upper surface of the first conductive layer is 150 nm or less.

In this case, it is possible to effectively improve the adhesion strength of the insulating layer to the first conductive layer without excessively roughening the first conductive layer.