A semiconductor device may include a substrate having a chip region and a scribe lane region, the chip region including a plurality of chips arranged in a first direction and in a second direction, the second direction crossing the first direction, the scribe lane region surrounding the chip region, a peripheral circuit structure on the substrate, the peripheral circuit structure including a transistor with a gate and an active region, a cell structure on the peripheral circuit structure, a protective layer on at least a portion of the cell structure, and a discharge structure penetrating through the cell structure in a third direction, the third direction crossing each of the first direction and the second direction, the discharge structure electrically connected to the substrate. An upper surface of the discharge structure is exposed to an outside of the cell structure.

Provided is an electronic device, which includes a substrate, a via, a conductive element and a circuit structure. The via penetrates through the substrate and includes a first via and a second via. The conductive element is disposed in the via and includes a first conductive element and a second conductive element. The first conductive element is disposed in the first via. The second conductive element is disposed in the second via. The circuit structure is disposed on the substrate and is electrically connected to the conductive element. In a first direction, there is a first spacing between the two adjacent first conductive elements. There is a second spacing between the two adjacent second conductive elements. The first spacing is greater than the second spacing.

A flip-chip package structure including a semiconductor chip and a carrier having a plurality of electrical connection pads is provided, in which the semiconductor chip is connected to second solders on the electrical connection pads of the carrier via first solders. The thickness of the insulating protective layer on the surface of the carrier changes according to the thickness of the first solder, the thickness of the second solder and the thickness of the electrical connection pad, so that it has a certain thickness to avoid bridging problems in the solders, and can also avoid problems with holes in the solders caused by excessive thickness.

An electronic device includes a substrate, a base substrate, a metal connection body, a support body, a metal body, and a via. The substrate includes one main surface with a functional element and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that the one main surface faces the base substrate. The metal body is in contact with the support body and includes at least a portion extending to outside the substrate in plan view from the support body. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

An interconnect substrate includes a core layer made of glass having one surface and another surface, a first through portion penetrating the core layer from the one surface to the another surface, a resin portion covering an inner wall surface of the first through portion, a first laminate including an interconnect layer and an insulating layer and disposed on the one surface of the core layer, and a second through portion penetrating the first laminate and the core layer, wherein the second through portion extends through an inside of the first through portion, and wherein at a position of penetration through the core layer, an inner wall surface of the second through portion is constituted by the resin portion.