Provided is a semiconductor device including a buffer die configured to communicate with an external device, a memory die stack including a plurality of memory dies stacked on the buffer die and connected to the buffer die through a plurality of through silicon vias, and a capacitor arranged on an upper portion of an uppermost memory die among the plurality of memory dies, wherein the capacitor surrounds at least some surfaces of the plurality of memory dies, when viewed in a top down view.

An electronic device includes a three-dimensionally non-planar mold body defining at least part of one of a non-planar side surface and an opposed non-planar side surface of the electronic device, an electrically conductive structure provided on one of the non-planar side surface and the opposing non-planar side surface, and at least one electric entity at least partially inside of the three-dimensionally non-planar mold body.

Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.

A package structure and a method of manufacturing a package structure are provided. The package structure includes a first substrate, a first electronic component, a second substrate and a second electronic component. The first electronic component is disposed over a first through hole of the first substrate. The first electronic component is electrically connected to a first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole. The second electronic component is disposed over a second through hole of the second substrate. The second electronic component is electrically connected to a second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.

A first integrated circuit (IC) die and a second IC die are bonded together in a stacked arrangement in a device package. The second IC die includes at least one bonding structure that is bonded to the first IC die. A barrier layer on sidewalls of a top portion of the bonding structure is removed and replaced with a dielectric liner that is formed on the sidewalls after the bonding structure is formed. The dielectric liner has a material removal rate (e.g., for processes such as CMP, grinding, and/or chemical-based surface cleaning) that is closer to the material removal rate of the bonding structure than the material removal rate of the barrier liner. This reduces the likelihood of the formation of voids in the bond between the first IC die and the second IC die that might otherwise occur due to excessive material removal from the bonding structure.

A package structure and method for forming the same are provided. The package structure includes a cooling substrate formed on a base substrate, and the cooling substrate includes a cooling device. The package structure includes a packaged semiconductor device formed on the cooling substrate, and the packaged semiconductor device includes a first die, and the cooling device is directly below the first die.

Disclosed herein are microelectronic assemblies and related devices and methods for alleviating stresses in through-glass vias by providing a photopolymer liner. In some embodiments, a microelectronic assembly may include a glass core with a through-glass via (TGV), where the TGV includes a conductive material; and a liner material between the glass core and the conductive material of the TGV, where the liner material includes a photopolymer. In some embodiments, a microelectronic assembly may include a glass layer; a cavity in a surface of the glass layer, the cavity having sidewalls; and a liner material on the sidewalls of the cavity, where the liner includes a photopolymer.

A stacked memory system includes a substrate including a first region and a second region, a base die and a core die group stacked in the first region, an integrated chip stacked on the core die group, and a connection die group connected between the integrated chip and the substrate in the second region.

This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.