A semiconductor package includes a first redistribution layer which includes a first face and a second face that are opposite to each other in a first direction, a first semiconductor chip on the second face, a second semiconductor chip on the second face a first mold film on the second face, and that covers the first semiconductor chip and the second semiconductor chip, and a bridge die disposed on the first face, and that electrically connects the first semiconductor chip and the second semiconductor chip, wherein the bridge die is covered with a second mold film.

A semiconductor device includes a circuit substrate, a first semiconductor element, a second semiconductor element, and a connection element. The circuit substrate includes a first pad. The first semiconductor element is disposed on the circuit substrate and includes a second pad and a third pad. The second semiconductor element is disposed on the circuit substrate. The connection element is disposed on the circuit substrate and electrically connects the first semiconductor element and the second semiconductor element. The connection element includes a fourth pad. The second pad is bonded to the first pad through a conductive material, and the third pad is directly bonded to the fourth pad.

A method of making an inverter comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

A semiconductor package and a semiconductor package assembly are provided. The semiconductor package includes an interconnect structure, a chip, a redistribution layer (RDL), a molding compound, and through mold vias (TMVs). The chip is arranged on and coupled to the interconnect structure. The RDL is arranged on and coupled to the chip. The molding compound is arranged on the interconnect structure and encapsulates the chip and the RDL. The TMVs pass through the molding compound and are connected between the RDL and the interconnect structure. The chip includes a back-side connect structure, a transistor layer, a front-side connect structure and a carrier. The back-side connect structure is connected to the interconnect structure. The transistor layer is located on the back-side connect structure. The front-side connect structure is located on the transistor layer. The first carrier is located on and coupled to the interconnect structure.

A thermal interface film is used between a semiconductor die and a heat sink. The thermal interface film includes at least two layers, a first layer with vertically oriented graphite and a second layer with horizontally oriented graphite. The thermal interface film directs heat away from the semiconductor die both upwards and outwards, spreading the heat over a larger surface area more quickly.

A semiconductor package includes a first redistribution structure, a first die above the first redistribution structure, a second die above the first die, a heat dissipation unit on side surfaces of the first die or the second die, and a second redistribution structure above the second die. The semiconductor package includes a first post protruding from an upper surface of the first redistribution structure and extending to a lower surface of the second redistribution structure, a second post connecting the heat dissipation unit with a heat dissipation redistribution structure as a thermal path, and a molding unit filling an empty space between the first redistribution structure and the second redistribution structure. An outer pad of the heat dissipation redistribution structure is exposed to an outside of the semiconductor package, and an inner pad of the heat dissipation redistribution structure is in contact with the second post.

A semiconductor package assembly comprises a first semiconductor package with a first semiconductor element and a first set of conductive patterns exposed thereon; an interposer mounted thereon via a set of interconnect structures, wherein the interposer has a second set of conductive patterns on its back surface aligned with the first set, electrically connected through the interconnects; and the interposer includes at least one opening extending through it; a second semiconductor package mounted on the front surface of the interposer; and a heat sink, comprising a back heat sink plate mounted thereon between the first package and the interposer, thermally coupled with the first semiconductor element; a front heat sink plate mounted thereon between the interposer and the second package, in contact with the interposer's front surface; and a heat sink plate connector extending through the opening, connecting the plates for heat transfer.

A semiconductor package includes a substrate, a die, a first bonding material, a second bonding material and a heat dissipation system. The die is connected to the substrate. The first bonding material is disposed on the substrate beside the die. The second bonding material is disposed on and covers the die. The heat dissipation system, having a bottom surface in contact with the second bonding material, is disposed on the second bonding material over the die and on the first bonding material on the substrate. The heat dissipation system is fixed to the substrate through the first bonding material. The bottom surface of the heat dissipation system is fixed to the die through the second bonding material with a bonding interface existing therebetween, and the bonding interface includes a first curved surface.

The chip package structure and a method are disclosed, comprising: a substrate, a first rewiring layer, a first chip, a dummy wafer, a laminate layer, a second rewiring layer, a second chip, a metal connection through-hole, and a heat dissipation element. By introducing a dummy wafer with a lower thermal expansion coefficient on both sides of the first chip, the mismatch of the thermal expansion coefficient of the encapsulation structure can be reduced, and the warping generated by the chip during the encapsulation process can be reduced. By forming a metal connecting post between the first chip and the second chip, a heat dissipation passage is established to further reduce the encapsulation thermal resistance and thus improve the heat dissipation efficiency of the chip, so as to form a chip encapsulation structure with a better heat dissipation performance by combining heat dissipation elements.

A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device includes a quantum chip and an interposer on which the quantum chip is located. The interposer includes an interposer substrate and an interposer wiring layer. The interposer wiring layer is disposed on a surface of the interposer substrate on a side on which the quantum chip is located. The interposer wiring layer includes, in at least a part thereof, a superconducting material layer formed of a superconducting material and a non-superconducting material layer formed of a non-superconducting material.