A semiconductor wafer transport apparatus includes a frame, a transport arm movably mounted to the frame and having at least one end effector movably mounted to the arm so the at least one end effector traverses, with the arm as a unit, in a first direction relative to the frame, and traverses linearly, relative to the transport arm, in a second direction, and an edge detection sensor mounted to the transport arm so the edge detection sensor moves with the transport arm as a unit relative to the frame, the edge detection sensor being a common sensor effecting edge detection of each wafer simultaneously supported by the end effector, wherein the edge detection sensor is configured so the edge detection of each wafer is effected by and coincident with the traverse in the second direction of each end effector on the transport arm.

Methods, systems, and devices for identification marking cavity filling for semiconductor packages are described. A semiconductor device may be formed to be relatively less susceptible to surface failures, including failure initiated by stress risers associated with identification markings. For example, a mold compound material may be formed over one or more semiconductor dies of the semiconductor device. One or more identification markings may be formed in the mold compound material based on forming one or more cavities into a surface of the material. A second material may be formed in the one or more cavities and may fill each of the cavities. The second material may be a crack-resistant material. The second material may be formed through one or more apertures of a stencil, or the second material may be formed by applying the second material over an entirety of the surface of the semiconductor device.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.

The invention provides a semiconductor overlay measurement method, which comprises the following steps: providing a wafer, wherein the wafer comprises a plurality of regions arranged in an array, wherein each region contains a product number pattern, and providing a system, wherein the system comprises a data pool, a plurality of English letter patterns and numeral patterns are stored in the data pool, and finding out English letter patterns and/or the numeral patterns conforming to the product number patterns from the data pool, and splicing some English letter patterns and/or some numeral patterns into an alignment mark pattern, inputting the alignment mark pattern into the system, and performing a first overlay step on the alignment mark pattern and each product number pattern on the wafer.

An integrated device package is disclosed. The integrated device package can include a carrier, an electronic component mounted on the carrier, a molding material disposed over the carrier, and an electromagnetic interference shield layer disposed over the molding material. The electronic component is at least partially disposed in the molding material. The electromagnetic interference shield layer is configured to shield the electronic component from a radio frequency signal. The electromagnetic interference shield layer has a thickness in a range between 2 m and 6 m. A surface of the electromagnetic interference shield layer includes an ink mark that has a thickness in a range between 5 m and 15 m, or a laser mark that has a depth in a range between 1 m and 2 m.

A display device according to an embodiment includes: a display panel; a first pad portion disposed on a lateral side of the display panel; and an information code disposed on the lateral side of the display panel.

An integrated device package is disclosed. The integrated device package can include a carrier, an electronic component mounted on the carrier, a molding material disposed over the carrier, and an electromagnetic interference shield layer disposed over the molding material. The electronic component is at least partially disposed in the molding material. At least a portion of the shield layer is in contact with the electronic component. The electromagnetic interference shield layer is configured to shield the electronic component from a radio frequency signal. A surface of the electromagnetic interference shield layer includes an ink mark or a laser mark.

The present disclosure provides a method that includes receiving a circuit layout that includes circuit features and a mark pattern to be formed on a same material layer over an integrated circuit (IC) substrate, the circuit features being longitudinally oriented along a first direction and being distanced from each other along a second direction that is orthogonal to the first direction; fragmenting the mark pattern to generate a fragmented mark pattern having fragmented mark features such that the fragmented mark features are configured in parallel and are longitudinally oriented along a third direction; and generating a modified circuit layout for circuit fabrication, the modified circuit layout including the circuit features and the fragmented mark pattern.