A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.

Disclosed is a wafer-scale chip structure including a semiconductor wafer and multiple dies on the semiconductor wafer. The dies can include at least two dies with different patterns of fill shapes. Also disclosed are wafer-scale chip design methods and systems. In the design methods and systems, post-chip layout wafer-level topography optimization is performed to, for example, minimize performance variations between dies of the same design within the wafer-scale chip. Specifically, across-wafer die placement and wafer-level topography information is used to custom design and/or select different patterns of fill shapes to be inserted into the layouts of dies placed at different locations across the wafer-scale chip (including different patterns to be inserted into the layouts of dies that have the same design) in order to generate a design that minimizes either all across-wafer thickness variations or at least across-wafer thickness variations associated with specific dies having the same specific design.

In order to have uniform dot holes even when a deep laser mark of approximately 100 m depth is formed, a silicon wafer having a crystal plane orientation of (100) has an identification mark configured by a plurality of dot holes on a surface with a surface roughness of 0.15 to 0.60 nm. A ratio between a length in a <100> direction and a length in a <110> direction of an opening of the dot hole on a wafer surface is 1 to 1.10, the length in the <100> direction of the opening is 80 m to 110 m, a depth of the dot hole in a cross-section is 80 m to 110 m, and a bottom surface of the dot hole is a flat surface of a (100) plane.

A semiconductor package includes a first package substrate. A first semiconductor device is mounted on an upper surface of the first package substrate. A first molding is disposed on the first package substrate and covers the first semiconductor device. A second package substrate is disposed on the first molding. At least one second semiconductor device is mounted on an upper surface of the second package substrate. A second molding covers the second semiconductor device. The second molding has a marking pattern in the first region. The second molding has an uneven structure having a plurality of trenches that define a plurality of column structures protruding from a second region on the second semiconductor device.

A display device according to an embodiment includes: a display panel; a first pad portion disposed on a lateral side of the display panel; and an information code disposed on the lateral side of the display panel.

The present disclosure provides a method for manufacturing a semiconductor device having a mark. The method includes: providing a substrate including a device region and a peripheral region adjacent to the device region; forming an interconnect layer over the substrate; depositing a first dielectric layer on the interconnect layer; forming a redistribution layer (RDL) over the first dielectric layer in the device region; depositing a second dielectric layer on the RDL in the device region and the first dielectric layer in the device region and the peripheral region; and removing portions of the second dielectric layer, the first dielectric layer and the interconnect structure in the peripheral region to form the mark in the peripheral region.

An interconnect substrate includes an insulating layer, a dispersion layer, and an interconnect layer, the insulating layer, the dispersion layer, and the interconnect layer being laminated together, wherein the dispersion layer includes a main material and one or more fillers dispersed in the main material, the one or more fillers forming a unique dispersion pattern, and wherein the unique dispersion pattern is identifiable by image recognition from outside of the interconnect substrate.

A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

A method of marking information on a substrate for use in a semiconductor component is provided. The method comprises providing a substrate for use in a semiconductor component, providing a metal layer on a surface of the substrate, and providing a marking within the metal layer. A method of making a die, a radio-frequency module and a wireless mobile device; as well as a substrate, a die, a radio-frequency module and a wireless mobile device is also provided.