Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a first surface, a second surface opposite the first surface, and a side surface extending between the first surface and the second surface, wherein the side surface protrudes at a middle of the glass layer; a dielectric layer at the first surface of the glass layer; and a recess in the dielectric layer at the first surface of the glass layer. In other embodiments, a microelectronic assembly may include a dielectric layer at a surface of a glass layer and a material along a side surface of the dielectric layer, the material including a dry film photoresist, a water-soluble material, a thermal decomposable material, or a non-filled polymeric material. In other embodiments, the dielectric layer may include a conductive bulk material along a side surface.

A semiconductor package includes a first substrate having a first and second bottom surfaces located at different vertical levels from a top surface of the first substrate, a first semiconductor chip on the top surface of the first substrate, a second semiconductor chip on the first bottom surface and including a photonic integrated circuit, and a second substrate on the second bottom surface to cover the second semiconductor chip. The first substrate includes: a first via vertically penetrating the first substrate and electrically connecting the first semiconductor chip to the second semiconductor chip; a second via vertically penetrating the first substrate and electrically connecting the first semiconductor chip to the second substrate; and an optical waveguide on the first bottom surface. A first distance from the top surface to the first bottom surface is smaller than a second distance from the top surface to the second bottom surface.

A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device includes a quantum chip and an interposer on which the quantum chip is located. The interposer includes an interposer substrate and an interposer wiring layer. The interposer wiring layer is disposed on a surface of the interposer substrate on a side on which the quantum chip is located. The interposer wiring layer includes, in at least a part thereof, a superconducting material layer formed of a superconducting material and a non-superconducting material layer formed of a non-superconducting material.

Assemblies and methods of manufacturing assemblies that include sockets and packaged semiconductor chips are provided. The packages for the semiconductor chips can include cores that are formed from a solid amorphous glass layer.

A core layer of a package substrate includes a sheet including glass; structures defining electrically conductive pathways within the sheet; and a saw street structure (SSS) at one or more lateral edges of the sheet, the SSS one or more oblong bodies in respective cavities defined in one or more lateral edges of the sheet, individual ones of the one or more oblong bodies extending in a direction along a thickness of the sheet, having a lateral edge surface facing away from the sheet, and comprising a material (SSS material) including at least one of a polymer or a metal. The core layer further includes a plurality of build-up layers on at least one of a top surface or a bottom surface of the core layer, the plurality of build-up layers electrically coupled to the electrically conductive pathways of the core layer.

An electronic power module is disclosed that forms external electrical connections without the use of a lead frame. Instead, various types of external connectors can be used, such as a press-fit pin assembly and an integrated connection post and power tap. Different methods of securing the external connectors to a multilayer substrate are also disclosed.

Embodiments disclosed herein include an apparatus that includes a scraping head that has an inner cavity with open ends and an open bottom. In an embodiment, the scraping head comprises an inner wall with a port through the inner wall, and an outer wall adjacent to the inner wall. In an embodiment, a gap is provided between the inner wall and the outer wall, and a vacuum line is fluidically coupled to the gap.

Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate. In an embodiment, a portion of the first substrate extends past edge surfaces of the second substrate and the third substrate. In an embodiment, a layer surrounds the portion of the first substrate, where the layer comprises a tapered cross-sectional shape, and where a first sidewall that contacts the second substrate and the third substrate has a first height that is greater than a second height of a second sidewall that faces away from the second substrate and the third substrate.

Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.