A base plate and power semiconductor module are provided, involving a basic body formed in one piece and having a front and rear side. The front side has a mounting area of the base plate. Along at least one of its edges, the basic body has at least one elevated integral part forming at least one sidewall projecting beyond the mounting area by a vertical height. At mounting area regions, the basic body has vertical thickness extending between the front and rear side and being larger than the vertical height of the sidewall. Along all edges, the basic body involves either at least one sidewall or at least one groove, but not both, at the same edge. Along at least one of its edges, the basic body involves one elevated integral part forming the at least one sidewall.

A base plate and power semiconductor module are provided, involving a basic body formed in one piece and having a front and rear side. The front side has a mounting area of the base plate. Along at least one of its edges, the basic body has at least one elevated integral part forming at least one sidewall projecting beyond the mounting area by a vertical height. At mounting area regions, the basic body has vertical thickness extending between the front and rear side and being larger than the vertical height of the sidewall. Along all edges, the basic body involves either at least one sidewall or at least one groove, but not both, at the same edge. Along at least one of its edges, the basic body involves one elevated integral part forming the at least one sidewall.

A semiconductor element bonding substrate according to the present invention includes an insulating plate, and a metal pattern bonded to a main surface of the insulating plate. A main surface of the metal pattern on an opposite side of the insulating plate includes a bonding region to which a semiconductor element is bonded by a solder. The metal pattern includes at least one concave part located in the main surface. The at least one concave part is located closer to an edge of the bonding region in relation to a center part of the bonding region in the bonding region.

An electronic device is provided. An example electronic device includes: a support structure including a substrate of dielectric material, a top conductive structure, arranged above the substrate, and a bottom conductive structure, arranged below the substrate, the top conductive structure including an annular region, the bottom conductive structure including an array of contacts; a cap coupled to the annular region such that the cap and the support structure delimit a cavity; and at least one semiconductive die in the cavity that generates one or more electric output signals. The array of contacts includes: signal contacts, which receive corresponding electric output signals or electric signals generated outside the electronic device; and reference contacts set to a reference potential. The electronic device further includes a plurality of reinforcement conductive vias, each extending through the substrate and has ends fixed respectively to the annular region and to a corresponding reference contact.

Provided is a semiconductor package including: a substrate including a first surface a and second surface opposite to the first surface, the substrate further including a first cavity extending from the first surface to the second surface; first and second lower semiconductor chips, wherein the first and second lower semiconductor chips are vertically stacked in the first cavity; a first redistribution substrate on the first surface of the substrate; a first upper semiconductor chip on the first redistribution substrate; a second upper semiconductor chip on the first redistribution substrate and horizontally spaced apart from the first upper semiconductor chip; and a first bridge chip in the first redistribution substrate that connects the first and second upper semiconductor chips, wherein the first lower semiconductor chip is spaced apart from the first redistribution substrate, and wherein the second lower semiconductor chip is directly connected to the first redistribution substrate.

Bonded die structures and methods of fabrication thereof that provide reduced defects and higher reliability. A laser grooving process may be used to precut bonded device structures prior to a final dicing process. The laser grooving process may form relatively deep grooves in the bonded device structure that may extend beyond the bonding interface between a first device structure and a second device structure. A final dicing process along the precut grooves may be used to separate individual bonded die structures. Because the dicing occurs along the deep precut grooves that extend through the bonding interface between the stacked device structures, the dicing blade may not cut through or come into contact with the bonding interface. This may result in in reduced mechanical stress, which may decrease the occurrence of delamination defects between the device structures and thereby provide improved reliability and increased yields.

A semiconductor package including a first package substrate having a first surface and a second surface, the second surface being opposite to the first surface; a first semiconductor chip on the second surface of the first package substrate; an interposer including a third surface and a fourth surface, the fourth surface being opposite to the third surface, and the third surface facing the first semiconductor chip; a second package substrate on the interposer, and a connection terminal being between the second package substrate and the interposer; and a second semiconductor chip on the second package substrate. The interposer defines a cavity that is an indentation in at least a portion of the fourth surface, and the connection terminal is in the cavity.

An apparatus including a stack of a plurality of substrates, wherein the stack includes a plurality of channels extending therethrough. The plurality of channels are configured to allow air to flow therethrough; a plurality of dynamic random-access memory (DRAM) chips. Respective ones of the plurality of DRAM chips are attached to one of the plurality of substrates and located within one of the plurality of channels. The apparatus also includes a plurality of processor chips located on an outer surface of the stack, and a plurality of wires electrically connecting the plurality of DRAM chips to the plurality of processor chips.

A semiconductor package includes: a package substrate including a first substrate region and a second substrate region, wherein the first substrate region at least partially surrounds the second substrate region; a semiconductor chip disposed on the package substrate; a mold provided on the package substrate and covering the semiconductor chip; and a shield provided on the mold and the package substrate, wherein a thickness of the first substrate region is smaller than a thickness of the second substrate region.

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.