A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.

Overhang architectures for high bandwidth memory (HBM) multi-die assemblies and methods for making same. The overhang architecture places the DRAM (HBM) underneath the top IC die. The signal interconnects between the top IC die and the DRAM die are direct signal interconnects without lateral routing on a package substrate or on a motherboard.

Some embodiments relate to an integrated device, including: a first interconnect structure on a first substrate; a first central bond pad coupled to the first interconnect structure; a first peripheral bond pad on a first side of the first central bond pad separated by a first distance; a second peripheral bond pad on a second side of the first central bond pad and separated by a second distance substantially equal to the first distance; a second interconnect structure on a second substrate; a first overlying bond pad coupled to the second interconnect structure and bonded to the first central bond pad; and a plurality of exposed bond pads respectively coupled to the first central bond pad, the first peripheral bond pad, the second peripheral bond pad, and the first overlying bond pad, wherein the plurality of exposed bond pads extend past outer sidewalls of the second substrate.

A package structure and a method for manufacturing the same, and an electronic device are provided. The package structure includes a substrate, a chip stack, a heat dissipation layer, and a molding layer. The chip stack is disposed on the substrate, the heat dissipation layer is disposed on the chip stack, and the molding layer is disposed on the substrate and covers the chip stack. The molding layer is in contact with the heat dissipation layer, the molding layer and the heat dissipation layer are coplanar, and the thermal conductivity coefficient of the plastic encapsulating layer is less than the thermal conductivity coefficient of the heat dissipation layer.

An electronic device realizes an antenna-in-package (AiP). The device includes a first die having a first metal layer that defines an antenna patch, a second metal layer that defines a parasitic patch above and vertically aligned with the antenna patch, and an amplifier having an output terminal electrically coupled to the antenna patch. The device further includes a second die having a metal layer that defines a reflecting patch and an interconnect that joins the first die with the second die in a vertical stack with the first die above the second die such that the antenna patch is spaced apart from, parallel to, and vertically aligned with the reflecting patch.

A reliability of a semiconductor device can be improved by measuring a value of a current flowing through a power transistor accurately. A semiconductor chip includes a power transistor and a source electrode electrically connected to a source region of the power transistor. The source electrode and a lead terminal are electrically connected to each other via a wire. The source electrode includes detection points for detecting the value of the current flowing through the power transistor. The detection points are arranged so as to sandwich a bonding point of the wire bonded to the source electrode.

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a semiconductor substrate and a second bonding structure over the semiconductor substrate. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. Sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate. The first connectors are in physical contact with the second connectors. The first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer. The encapsulant laterally encapsulates the second die. The TIVs are aside the second die.

A semiconductor package structure includes a first redistribution layer, a second redistribution layer, a first semiconductor die, a second semiconductor die, an adhesive layer, and a molding material. The second redistribution layer is disposed over the first redistribution layer. The first semiconductor die and the second semiconductor die are stacked vertically between the first redistribution layer and the second redistribution layer. The first semiconductor die is electrically coupled to the first redistribution layer, and the second semiconductor die is electrically coupled to the second redistribution layer. The adhesive layer extends between the first semiconductor die and the second semiconductor die. The molding material surrounds the first semiconductor die, the adhesive layer, and the second semiconductor die.

A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.