A technique increases verticality in etching. An etching method is a method for etching a target film with a plasma processing apparatus including a chamber and a substrate support located in the chamber to support a substrate, the substrate support holding a substrate that includes the target film, the target film including a patterned mask film having at least one opening. The etching method includes supplying a process gas containing an HF gas into the chamber, and etching the target film by: generating plasma from the process gas in the chamber with radio-frequency power having a first frequency, and applying a pulsed voltage periodically to the substrate support at a second frequency lower than the first frequency.

Molybdenum is etched in a highly controllable manner by performing one or more etch cycles, where each cycle involves exposing the substrate having a molybdenum layer to an oxygen-containing reactant to form molybdenum oxide followed by treatment with boron trichloride to convert molybdenum oxide to a volatile molybdenum oxychloride with subsequent treatment of the substrate with a fluorine-containing reactant to remove boron oxide that has formed in a previous reaction, from the surface of the substrate. In some embodiments the method is performed in an absence of plasma and results in a substantially isotropic etching. The method can be used in a variety of applications in semiconductor processing, such as in wordline isolation in 3D NAND fabrication.

The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

Methods for etching metal, such as for processing a metal gate, are provided. A method includes forming a hard mask over the metal, wherein the hard mask includes a sidewall defining an opening; and performing a plasma etching process including cycles of depositing a carbon nitride film on the sidewall and etching the metal.

A multilayer wiring connection structure and a method for manufacturing the same are provided. The multilayer wiring connection structure includes a first insulating film positioned on a substrate, a first wiring positioned within the first insulating film, a second insulating film positioned on the first wiring, and a second wiring positioned within the second insulating film and in contact with the first wiring. The first wiring comprises a trench having at least one anisotropically etched portion and at least one isotropically etched portion under the second wiring, and the second wiring comprises an extension filling the trench.

A method may include providing a first hardmask and a second hardmask over a metal line layer, wherein the metal line layer is formed over a dielectric layer, and forming a plurality of trenches through the first hardmask and the second hardmask, wherein each of the plurality of trenches is defined by a first main side opposite a second main side, and a first end opposite a second end. The method may further include performing a plasma etch to remove a portion of the first hardmask and the second hardmask from the first end or the second end of each of the plurality of trenches, wherein the plasma etch comprises directing ions into the plurality of trenches at a non-zero angle relative to a perpendicular extending from an upper surface of the second hardmask.

A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

A method of capping a metal layer includes performing a conversion process to reduce a metal oxide layer formed on a top surface of the metal layer and form a metal sulfide layer on the top surface of the metal layer, exposing the top surface of the metal layer to an oxidizing environment, and performing a removal process to remove the metal sulfide layer.

Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.