A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

A package structure is provided. The package structure includes a substrate, a first electronic component, an encapsulant, and a protective element. The first electronic component is over the substrate. The encapsulant is over the substrate and defines a cavity that exposes the first electronic component. The protective element covers the first electronic component. A lateral surface of the protective element is substantially aligned with a lateral surface of the encapsulant.

An electronic component includes a plurality of laminated insulating layers, one or more surface conductors formed on a surface of the insulating layer, and an internal conductor formed at a boundary portion between the adjacent insulating layers. A thickness of the surface conductor is larger than a thickness of a thinnest layer of the insulating layers and larger than a thickness of the internal conductor.

A universal structure for achieving a 360-degree spatial light emission in a white or monochromatic light LED, including: an LED direct insertion holder, an LED chip, wires, and chip bonding material, LED concapsulation gel, chip forming gel, an auxiliary material, the chip bonding material is placed on a solid crystal position of the LED direct insertion holder, the LED chip is fixedly connected to the LED direct insertion holder through the chip bonding material, the LED chip is electrically connected to the LED direct insertion holder via the wire; the chip forming gel is applied at the solid crystal position of the LED direct insertion holder, an LED reflective cup or a flat cup structure is provided inside the LED direct insertion holder. This disclosure addresses the issues of the existing LED concapsulation structure lacking versatility, having a complex concapsulation process, and producing low light quality levels.

An electronic device package includes a frame, an electronic device mounted to the frame, surface-mount leads, and a gel at least partially filling a cavity between the electronic device and the frame. The electronic device includes electronic circuitry provided on an electronic device substrate, and the surface-mount leads are electrically connected to the electronic circuitry and extend laterally and outwardly from an outer perimeter of the frame. The gel in the cavity covers the electronic circuitry.

An electronic device includes a semiconductor die having a first side attached to a substrate, a first plate having a first portion attached to a second side of the semiconductor die and a second portion extending from the first portion away from the semiconductor die, a metal clip having a second clip portion coupled to a first conductive feature of the substrate, a third clip portion coupled to a second conductive feature of the substrate, and a first clip portion above and spaced apart from the first portion of the first plate that extends between the second and third clip portions, a magnetic molding compound package structure enclosing the metal clip, the semiconductor die, and the first portion of the first plate, and a second plate exposed outside the package structure and thermally coupled to the second portion of the first plate.

A semiconductor device has a substrate and an electrical component disposed over the substrate. A first encapsulant is deposited over the electrical component and substrate. A first shielding layer with a graphene core shell is formed on a surface of the first encapsulant. A second encapsulant is deposited over the first encapsulant and first shielding layer. A second shielding layer is formed over the second encapsulant. The first shielding layer is formed at least partially in an opening of the first encapsulant. The graphene core shell has a copper core. The first shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the first shielding layer to form an electrical path. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.

A semiconductor device has a substrate and an electrical component disposed over the substrate. A first encapsulant is deposited over the electrical component and substrate. A first shielding layer with a graphene core shell is formed on a surface of the first encapsulant. A second encapsulant is deposited over the first encapsulant and first shielding layer. A second shielding layer is formed over the second encapsulant. The first shielding layer is formed at least partially in an opening of the first encapsulant. The graphene core shell has a copper core. The first shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the first shielding layer to form an electrical path. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.

In an embodiment, a method includes forming a package structure, where forming the package structure includes attaching a plurality of dies to a carrier substrate, performing an encapsulation process to surround the plurality of dies with an encapsulant, and forming a redistribution structure over the plurality of dies and the encapsulant, where the redistribution structure is electrically connected to the plurality of dies, where the redistribution structure has a rectangular shape when seen in a top-down view, where the rectangular shape has first parallel edges having a first width, and second parallel edges having a second width, where at least one of the first width and the second width is greater than 212 mm.