The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.

A protective film forming agent that, in dicing of a semiconductor wafer, is used to form a protective film on the surface of the semiconductor wafer, can form a protective film that has excellent laser processability, and has excellent solubility of a light-absorbing agent; and a method for producing a semiconductor chip using the protective film forming agent. The protective film forming agent includes a water-soluble resin, a light-absorbing agent, a basic compound, and a solvent. The basic compound is an alkylamine, an alkanolamine, an imidazole compound, ammonia, or an alkali metal hydroxide. The light-absorbing agent content of the protective film forming agent is 0.1-10 mass % (inclusive).

A semiconductor structure includes: a semiconductor substrate; a gate dielectric layer over the semiconductor substrate; and a gate electrode over the gate dielectric layer. The gate dielectric layer includes a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion includes a third portion including nitrogen and enclosed by the first portion.

Provided are compositions and methods for the wet etching of a surface of a microelectronic device substrate which contains surfaces comprising silicon nitride, silicon oxide, and polysilicon. The method of the invention involves a passivation step and a silicon nitride etching step, as more fully described below. The combination of the two steps was found to greatly improve the selectivity of the silicon nitride etching operation in the presence of polysilicon.

Aspects of the present disclosure provide an inhibitor-free method for filling a recessed feature of a substrate. For example, the inhibitor-free method can include providing a substrate that has a recessed feature, forming a first layer of an insulating material on the substrate to cover a sidewall and bottom of the recessed feature, removing a portion of the first layer such that the recessed feature with the first layer remaining therein slopes outward, and forming a second layer of the insulating material on the substrate to cover the first layer remaining in the recessed feature.

The present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A diamond-like carbon hard mask layer is formed on a substrate, in which an absorbance of the diamond-like carbon hard mask layer is smaller than or equal to 0.5. A dielectric anti-reflective coating layer is formed on the diamond-like carbon hard mask layer. A bottom anti-reflective coating layer is formed on the dielectric anti-reflective coating layer.

The present disclosure provides a method for manufacturing a semiconductor device having a mark. The method includes: providing a substrate including a device region and a peripheral region adjacent to the device region; forming an interconnect layer over the substrate; depositing a first dielectric layer on the interconnect layer; forming a redistribution layer (RDL) over the first dielectric layer in the device region; depositing a second dielectric layer on the RDL in the device region and the first dielectric layer in the device region and the peripheral region; and removing portions of the second dielectric layer, the first dielectric layer and the interconnect structure in the peripheral region to form the mark in the peripheral region.

There is a method for making a substrate by providing a Si top surface in a plane, and providing a GaN top surface in the plane adjacent the Si top surface, wherein a substrate is formed having a top surface comprising the Si top surface and the GaN top surface. There is a substrate having a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface. There is a package having a substrate with a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface, a CMOS chip attached to the Si top surface, a GaN transistor attached to the GaN top surface, and a metal layer connecting the CMOS chip and the GaN transistor.

Provided is an etching solution composition that can have both a higher etch selectivity of silicon nitride and a reduction in the deposition of silica on the surface of silicon oxide. An inorganic acid-based etching solution composition for selectively etching away silicon nitride from a semiconductor containing silicon nitride and silicon oxide, the etching solution composition comprising: (a) an etch inhibitor that reduces etching of silicon oxide; and (b) a deposition inhibitor that reduces deposition of silica on a surface of silicon oxide.

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.