A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The methods may include contacting a substrate housed in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron-and-nitrogen-containing material overlying a carbon-containing material. The boron-and-nitrogen-containing material comprises a plurality of openings. The methods may include etching the carbon-containing material.

Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

A method of forming a line cut structure in a space separating lines of a line pattern formed in or on a substrate includes conformally depositing a conformal layer on at least one sidewall of a cut window in a resist layer and through the cut window on a portion of the space, etching the conformal layer from horizontal surfaces of the substrate leaving a cut sidewall spacer on the at least one sidewall, and removing the resist layer to form the line cut structure from the cut sidewall spacer. The method may further include forming a metal cut in a metal line by etching a dielectric layer to transfer the line pattern and the line cut structure into the dielectric layer forming a dielectric line cut structure and then forming a metal layer including the metal line in the dielectric layer.

A semiconductor structure and a method for fabricating the semiconductor structure are provided in the present disclosure. The method includes providing a substrate, wherein the substrate includes a plurality of first regions to-be-etched extending along a first direction; a first region to-be-etched includes a central region and an edge region adjacent to each of two sides of the central region; and a material layer to-be-etched is on the substrate; forming a plurality of discrete initial mask structures on the material layer to-be-etched; etching initial mask structures at the edge region till a surface of the material layer to-be-etched is exposed to form a plurality of mask structures; using the plurality of mask structures as a mask, etching the material layer to-be-etched to form a plurality of discrete layers to-be-etched; and removing layers to-be-etched at the central region till a surface of the substrate is exposed.

The present disclosure provides a method of forming a patterned structure. The method includes the following operations. A photoresist layer on a target layer is patterned to form a first opening in a patterned photoresist layer. A directed self-assembly layer is formed on the patterned photoresist layer and in the first opening, in which a directed self-assembly material in the directed self-assembly layer separates into a first phase on the patterned photoresist layer and a second phase in the first opening by the first phase being attracted by a polarity of the patterned photoresist layer. The second phase is removed to form a second opening through the directed self-assembly layer. The target layer is etched through the second opening.

A method for processing a substrate includes receiving the substrate on a substrate holder, the substrate including a patterned mask disposed over a patterned underlying layer, the patterned mask including notches. The method further includes having a plurality of polar angles and a plurality of processing times, each of the plurality of polar angles having an associated one of the plurality of processing times, and processing the substrate with a cyclic process for each of the plurality of polar angles. Each cycle of the cyclic process includes selecting a polar angle (.sub.i) from the plurality of polar angles. Each cycle further includes tilting a processing tool such that a beam emitted from the processing tool strikes the substrate at the selected polar angle (.sub.i), and emitting the beam at the selected polar angle (.sub.i) for an i.sup.th timeframe (t.sub.i) corresponding to the selected polar angle (.sub.i) to deposit an i.sup.th layer over the notches.

A semiconductor structure includes: a semiconductor substrate; a gate dielectric layer over the semiconductor substrate; and a gate electrode over the gate dielectric layer. The gate dielectric layer includes a first portion and a second portion thinner than the first portion, wherein the gate electrode is over the first portion and the second portion, and the first portion includes a third portion including nitrogen and enclosed by the first portion.

First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.