A lighting device disclosed in an embodiment of this invention includes a reflective layer, a resin layer disposed on the reflective layer, a substrate disposed on the resin layer and including an electrode layer, a plurality of light emitting devices disposed between the resin layer and the substrate, and a light blocking layer disposed on the substrate, the electrode layer may include a first pattern region disposed adjacent to the light emitting device and a second pattern region disposed outside the first pattern region and having a pattern different in size from the first pattern region, and the light blocking pattern region may overlap in a vertical direction with the first pattern region.

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

A semiconductor structure may be provided by forming a first molding compound around a first semiconductor die such that a top surface of the first molding compound is coplanar with a top dielectric surface of the first semiconductor die; forming a combination of at least one bonding-level dielectric layer, first bonding pads, and dummy pads over the first semiconductor die and the first molding compound, wherein each of the bonding pads is formed directly on a respective conductive structure within the first semiconductor die; and attaching a second semiconductor die including second bonding pads therein to the first semiconductor die by performing a bonding process that bonds the second bonding pads to the first bonding pads by metal-to-metal bonding such that a first subset of the dummy pads has an areal overlap in a plan view with the second semiconductor die.

A package substrate structure includes a package substrate, first and second substrate pads, and first and second wiring structures. The package substrate has first and second surfaces opposite to each other in a vertical direction. The first and second substrate pads are at the same level as each other in the package substrate, and adjacent to the first surface of the package substrate. The first wiring structure is in the package substrate. At least a portion of the first wiring structure is at the same level as and contacts the first substrate pad. The second wiring structure is in the package substrate. At least a portion of the second wiring structure is at the same level as and contacts the second substrate pad. The second wiring structure has an extension length greater than an extension length of the first wiring and a width smaller than a width of the first wiring.

A semiconductor substrate including a front side and a backside and including a good die region having a plurality of semiconductor chips, a dummy die region having a plurality of dummy chips in an arc shape along an outer portion of the good die region, a plurality of first bump pads at a first interval on the backside of each of the plurality of semiconductor chips, and a plurality of second bump pads at a second interval on the backside of at least one of the plurality of dummy chips. The second interval is smaller than the first interval. The plurality of first bump pads are in a first matrix arrangement and the plurality of second bump pads are alternately arranged in a second matrix arrangement, the second matrix arrangement including both the first matrix arrangement and the first matrix arrangement shifted by a desired distance in a horizontal direction.

A display device may include: a substrate including a display area having first to third areas, and a non-display area; first pixels in the first area, second pixels in the second area, and third pixels in the third area; a pad part located in the non-display area, and electrically connected to the first to third pixels; a line part including a first line between the pad part and the first area, a second line between the pad part and the second area, and a third line between the pad part and the second area; a bridge line extending in a first direction, and located in the second and third areas; and an extension line extending in a second direction, and located in the second area and electrically connected with the bridge line. The extension line may be electrically connected with the third line.

A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

A stacked semiconductor device includes first chips and a second chip. The first chips are arranged in an array, and includes first and second type through vias, an internal wire layer, a redistribution line and conductive pins. The internal wire layer is disposed on and electrically connected to the first and second type through vias. The redistribution line is disposed on and electrically connected to the second type through vias and the internal wire layer, wherein the redistribution line extends from a top surface of the second type through vias to a position non-overlapped with the second type through vias. The conductive pins are disposed on and electrically connected to the redistribution line. The second chip is stacked on the first chips, wherein the second chip includes connection pins, and the second chip is connected to the first chips by bonding the connection pins to the conductive pins.

A fan-out semiconductor package includes a semiconductor chip; a metal pillar disposed on the semiconductor chip; a bonding metal layer disposed on the metal pillar; a bonding wire disposed on the bonding metal layer; a sealing layer over the semiconductor chip, and surrounding the metal pillar, the bonding metal layer, and the bonding wire; and a redistribution layer disposed on the sealing layer and the bonding wire.

Disclosed is a bonded structure including a first microelectronic structure with a first bonding surface and a second microelectronic structure with a second bonding surface directly bonded to the first bonding surface. The first microelectronic structure includes at least one cavity a through the first bonding surface. The second microelectronic structure includes at least one protrusion extending above the second bonding surface. The at least one protrusion of the second microelectronic structure extends within the at least one cavity of the first microelectronic structure without reaching a bottom of the at least one cavity.