A semiconductor die is arranged at a mounting region of a surface of a substrate. A substrate includes electrically conductive leads around a die pad including a mounting region. A metallic layer is located at one or more portions of the substrate including the mounting region. A semiconductor die is arranged at a mounting region. The metallic layer is selectively exposed at portions less than all of the metallic layer to an oxidizing plasma to produce a patterned oxide layer including oxides of metallic material in the metallic layer. An electrically insulating encapsulation is molded onto the surface of the substrate to encapsulate the semiconductor die. The oxides of metallic material in the patterned oxide layer facilitate adhesion of the electrically insulating encapsulation to the surface of the substrate.

Barrier-free interconnects and methods of fabrication thereof are disclosed herein. An exemplary interconnect structure has a conductive line disposed over a conductive via. The conductive line has a first conductive plug disposed in a first dielectric layer, and the first conductive plug includes an electrically conductive non-metal material, such as graphite. The conductive via includes a second conductive plug disposed in a second dielectric layer, and the second conductive plug includes a metal material, such as tungsten, ruthenium, molybdenum, or combinations thereof. The first conductive plug physically contacts the second conductive plug and the second dielectric layer. The second conductive plug physically contacts the second dielectric layer. Spacers (which are insulators) may be disposed between sidewalls of the first conductive plug and the first dielectric layer. The spacers may further be disposed between the first dielectric layer and the second dielectric layer.

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.

Disclosed are a semiconductor photoresist composition and a method of forming patterns using the semiconductor photoresist composition. The semiconductor photoresist composition includes an organometallic compound represented by Chemical Formula 1 and a solvent and a method of forming patterns using the same.

An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

An etching method includes: a) preparing, within a chamber, a substrate including a mask film containing ruthenium and having a predetermined pattern formed in the mask film, and a silicon-containing film provided under the mask film; b) supplying a process gas including a hydrocarbon-containing gas and a fluorine-containing gas into the chamber; and c) etching the silicon-containing film through the mask film using plasma generated from the process gas supplied into the chamber.

A method of manufacturing a semiconductor device including forming a target layer, forming a pre-modification carbon layer over the target layer, modifying and patterning the pre-modification carbon layer to form a post-modification carbon mask pattern by performing a modification process and a patterning process, and forming trenches in the target layer by performing an etching process using the post-modification carbon mask pattern as an etching mask.

Provided are a resist compound, a method of forming a pattern by using the same, and a method of manufacturing a semiconductor device using the same. According to the present disclosure, the compound may be represented by Formula 1: ##STR00001##

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

Methods for the fabrication of semiconductor devices are disclosed. A method may include depositing a mask layer on a substrate, forming a protection layer on the mask layer, and modifying the protection layer such that a porosity of the protection layer is reduced. Modifying the protection layer may include densifying the protection layer. Modifying the protection layer may include reducing the protection layer using a hydrogen plasma. The method may include etching the protection layer and the substrate. Etching may include etching, forming the protection layer, and modifying the protection layer in a predetermined number of cycles.